xref: /linux/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
8
9maintainers:
10  - Sibi Sankar <quic_sibis@quicinc.com>
11
12description:
13  The CPUSS Control Processor (CPUCP) mailbox controller enables communication
14  between AP and CPUCP by acting as a doorbell between them.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,glymur-cpucp-mbox
22          - const: qcom,x1e80100-cpucp-mbox
23      - enum:
24          - qcom,x1e80100-cpucp-mbox
25
26  reg:
27    items:
28      - description: CPUCP rx register region
29      - description: CPUCP tx register region
30
31  interrupts:
32    maxItems: 1
33
34  "#mbox-cells":
35    const: 1
36
37required:
38  - compatible
39  - reg
40  - interrupts
41  - "#mbox-cells"
42
43additionalProperties: false
44
45examples:
46  - |
47    #include <dt-bindings/interrupt-controller/arm-gic.h>
48
49    mailbox@17430000 {
50        compatible = "qcom,x1e80100-cpucp-mbox";
51        reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
52        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
53        #mbox-cells = <1>;
54    };
55