xref: /linux/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1*6e7c4cc5SSibi Sankar# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2*6e7c4cc5SSibi Sankar%YAML 1.2
3*6e7c4cc5SSibi Sankar---
4*6e7c4cc5SSibi Sankar$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
5*6e7c4cc5SSibi Sankar$schema: http://devicetree.org/meta-schemas/core.yaml#
6*6e7c4cc5SSibi Sankar
7*6e7c4cc5SSibi Sankartitle: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
8*6e7c4cc5SSibi Sankar
9*6e7c4cc5SSibi Sankarmaintainers:
10*6e7c4cc5SSibi Sankar  - Sibi Sankar <quic_sibis@quicinc.com>
11*6e7c4cc5SSibi Sankar
12*6e7c4cc5SSibi Sankardescription:
13*6e7c4cc5SSibi Sankar  The CPUSS Control Processor (CPUCP) mailbox controller enables communication
14*6e7c4cc5SSibi Sankar  between AP and CPUCP by acting as a doorbell between them.
15*6e7c4cc5SSibi Sankar
16*6e7c4cc5SSibi Sankarproperties:
17*6e7c4cc5SSibi Sankar  compatible:
18*6e7c4cc5SSibi Sankar    items:
19*6e7c4cc5SSibi Sankar      - const: qcom,x1e80100-cpucp-mbox
20*6e7c4cc5SSibi Sankar
21*6e7c4cc5SSibi Sankar  reg:
22*6e7c4cc5SSibi Sankar    items:
23*6e7c4cc5SSibi Sankar      - description: CPUCP rx register region
24*6e7c4cc5SSibi Sankar      - description: CPUCP tx register region
25*6e7c4cc5SSibi Sankar
26*6e7c4cc5SSibi Sankar  interrupts:
27*6e7c4cc5SSibi Sankar    maxItems: 1
28*6e7c4cc5SSibi Sankar
29*6e7c4cc5SSibi Sankar  "#mbox-cells":
30*6e7c4cc5SSibi Sankar    const: 1
31*6e7c4cc5SSibi Sankar
32*6e7c4cc5SSibi Sankarrequired:
33*6e7c4cc5SSibi Sankar  - compatible
34*6e7c4cc5SSibi Sankar  - reg
35*6e7c4cc5SSibi Sankar  - interrupts
36*6e7c4cc5SSibi Sankar  - "#mbox-cells"
37*6e7c4cc5SSibi Sankar
38*6e7c4cc5SSibi SankaradditionalProperties: false
39*6e7c4cc5SSibi Sankar
40*6e7c4cc5SSibi Sankarexamples:
41*6e7c4cc5SSibi Sankar  - |
42*6e7c4cc5SSibi Sankar    #include <dt-bindings/interrupt-controller/arm-gic.h>
43*6e7c4cc5SSibi Sankar
44*6e7c4cc5SSibi Sankar    mailbox@17430000 {
45*6e7c4cc5SSibi Sankar        compatible = "qcom,x1e80100-cpucp-mbox";
46*6e7c4cc5SSibi Sankar        reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
47*6e7c4cc5SSibi Sankar        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
48*6e7c4cc5SSibi Sankar        #mbox-cells = <1>;
49*6e7c4cc5SSibi Sankar    };
50