1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Global Command Engine Mailbox 8 9maintainers: 10 - Houlong Wei <houlong.wei@mediatek.com> 11 12description: 13 The Global Command Engine (GCE) is used to help read/write registers with 14 critical time limitation, such as updating display configuration during the 15 vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. 16 17properties: 18 compatible: 19 enum: 20 - mediatek,mt6779-gce 21 - mediatek,mt8173-gce 22 - mediatek,mt8183-gce 23 - mediatek,mt8186-gce 24 - mediatek,mt8192-gce 25 - mediatek,mt8195-gce 26 27 "#mbox-cells": 28 const: 2 29 description: 30 The first cell describes the Thread ID of the GCE, 31 the second cell describes the priority of the GCE thread 32 33 reg: 34 maxItems: 1 35 36 interrupts: 37 maxItems: 1 38 39 clocks: 40 items: 41 - description: Global Command Engine clock 42 43 clock-names: 44 items: 45 - const: gce 46 47required: 48 - compatible 49 - "#mbox-cells" 50 - reg 51 - interrupts 52 - clocks 53 54allOf: 55 - if: 56 not: 57 properties: 58 compatible: 59 contains: 60 const: mediatek,mt8195-gce 61 then: 62 required: 63 - clock-names 64 65additionalProperties: false 66 67examples: 68 - | 69 #include <dt-bindings/clock/mt8173-clk.h> 70 #include <dt-bindings/interrupt-controller/arm-gic.h> 71 #include <dt-bindings/interrupt-controller/irq.h> 72 73 soc { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 77 gce: mailbox@10212000 { 78 compatible = "mediatek,mt8173-gce"; 79 reg = <0 0x10212000 0 0x1000>; 80 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 81 #mbox-cells = <2>; 82 clocks = <&infracfg CLK_INFRA_GCE>; 83 clock-names = "gce"; 84 }; 85 }; 86