xref: /linux/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml (revision b8265621f4888af9494e1d685620871ec81bc33d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX Messaging Unit (MU)
8
9maintainers:
10  - Dong Aisheng <aisheng.dong@nxp.com>
11
12description: |
13  The Messaging Unit module enables two processors within the SoC to
14  communicate and coordinate by passing messages (e.g. data, status
15  and control) through the MU interface. The MU also provides the ability
16  for one processor to signal the other processor using interrupts.
17
18  Because the MU manages the messaging between processors, the MU uses
19  different clocks (from each side of the different peripheral buses).
20  Therefore, the MU must synchronize the accesses from one side to the
21  other. The MU accomplishes synchronization using two sets of matching
22  registers (Processor A-facing, Processor B-facing).
23
24properties:
25  compatible:
26    oneOf:
27      - const: fsl,imx6sx-mu
28      - const: fsl,imx7ulp-mu
29      - const: fsl,imx8-mu-scu
30      - items:
31          - enum:
32            - fsl,imx7s-mu
33            - fsl,imx8mq-mu
34            - fsl,imx8mm-mu
35            - fsl,imx8mn-mu
36            - fsl,imx8mp-mu
37            - fsl,imx8qxp-mu
38          - const: fsl,imx6sx-mu
39      - description: To communicate with i.MX8 SCU with fast IPC
40        items:
41          - const: fsl,imx8qxp-mu
42          - const: fsl,imx8-mu-scu
43
44  reg:
45    maxItems: 1
46
47  interrupts:
48    maxItems: 1
49
50  "#mbox-cells":
51    description: |
52      <&phandle type channel>
53      phandle   : Label name of controller
54      type      : Channel type
55      channel   : Channel number
56
57      This MU support 4 type of unidirectional channels, each type
58      has 4 channels. A total of 16 channels. Following types are
59      supported:
60      0 - TX channel with 32bit transmit register and IRQ transmit
61          acknowledgment support.
62      1 - RX channel with 32bit receive register and IRQ support
63      2 - TX doorbell channel. Without own register and no ACK support.
64      3 - RX doorbell channel.
65    const: 2
66
67  clocks:
68    maxItems: 1
69
70  fsl,mu-side-b:
71    description: boolean, if present, means it is for side B MU.
72    type: boolean
73
74required:
75  - compatible
76  - reg
77  - interrupts
78  - "#mbox-cells"
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85
86    mailbox@5d1b0000 {
87        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
88        reg = <0x5d1b0000 0x10000>;
89        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
90        #mbox-cells = <2>;
91    };
92