1*621d7d08SGuomin Chen# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*621d7d08SGuomin Chen%YAML 1.2 3*621d7d08SGuomin Chen--- 4*621d7d08SGuomin Chen$id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml# 5*621d7d08SGuomin Chen$schema: http://devicetree.org/meta-schemas/core.yaml# 6*621d7d08SGuomin Chen 7*621d7d08SGuomin Chentitle: Cixtech mailbox controller 8*621d7d08SGuomin Chen 9*621d7d08SGuomin Chenmaintainers: 10*621d7d08SGuomin Chen - Guomin Chen <Guomin.Chen@cixtech.com> 11*621d7d08SGuomin Chen 12*621d7d08SGuomin Chendescription: 13*621d7d08SGuomin Chen The Cixtech mailbox controller, used in the Cixtech Sky1 SoC, 14*621d7d08SGuomin Chen is used for message transmission between multiple processors 15*621d7d08SGuomin Chen within the SoC, such as the AP, PM, audio DSP, SensorHub MCU, 16*621d7d08SGuomin Chen and others 17*621d7d08SGuomin Chen 18*621d7d08SGuomin Chen Each Cixtech mailbox controller is unidirectional, so they are 19*621d7d08SGuomin Chen typically used in pairs-one for receiving and one for transmitting. 20*621d7d08SGuomin Chen 21*621d7d08SGuomin Chen Each Cixtech mailbox supports 11 channels with different transmission modes 22*621d7d08SGuomin Chen channel 0-7 - Fast channel with 32bit transmit register and IRQ support 23*621d7d08SGuomin Chen channel 8 - Doorbell mode,using the mailbox as an interrupt-generating 24*621d7d08SGuomin Chen mechanism. 25*621d7d08SGuomin Chen channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support 26*621d7d08SGuomin Chen channel 10 - Reg based channel with 32*32bit transmit register and 27*621d7d08SGuomin Chen Doorbell+transmit acknowledgment IRQ support 28*621d7d08SGuomin Chen 29*621d7d08SGuomin Chen In the CIX Sky1 SoC use case, there are 4 pairs of mailbox controllers 30*621d7d08SGuomin Chen AP <--> PM - using Doorbell transfer mode 31*621d7d08SGuomin Chen AP <--> SE - using REG transfer mode 32*621d7d08SGuomin Chen AP <--> DSP - using FIFO transfer mode 33*621d7d08SGuomin Chen AP <--> SensorHub - using FIFO transfer mode 34*621d7d08SGuomin Chen 35*621d7d08SGuomin Chenproperties: 36*621d7d08SGuomin Chen compatible: 37*621d7d08SGuomin Chen const: cix,sky1-mbox 38*621d7d08SGuomin Chen 39*621d7d08SGuomin Chen reg: 40*621d7d08SGuomin Chen maxItems: 1 41*621d7d08SGuomin Chen 42*621d7d08SGuomin Chen interrupts: 43*621d7d08SGuomin Chen maxItems: 1 44*621d7d08SGuomin Chen 45*621d7d08SGuomin Chen "#mbox-cells": 46*621d7d08SGuomin Chen const: 1 47*621d7d08SGuomin Chen 48*621d7d08SGuomin Chen cix,mbox-dir: 49*621d7d08SGuomin Chen $ref: /schemas/types.yaml#/definitions/string 50*621d7d08SGuomin Chen description: Direction of the mailbox relative to the AP 51*621d7d08SGuomin Chen enum: [tx, rx] 52*621d7d08SGuomin Chen 53*621d7d08SGuomin Chenrequired: 54*621d7d08SGuomin Chen - compatible 55*621d7d08SGuomin Chen - reg 56*621d7d08SGuomin Chen - interrupts 57*621d7d08SGuomin Chen - "#mbox-cells" 58*621d7d08SGuomin Chen - cix,mbox-dir 59*621d7d08SGuomin Chen 60*621d7d08SGuomin ChenadditionalProperties: false 61*621d7d08SGuomin Chen 62*621d7d08SGuomin Chenexamples: 63*621d7d08SGuomin Chen - | 64*621d7d08SGuomin Chen #include <dt-bindings/interrupt-controller/arm-gic.h> 65*621d7d08SGuomin Chen 66*621d7d08SGuomin Chen soc { 67*621d7d08SGuomin Chen #address-cells = <2>; 68*621d7d08SGuomin Chen #size-cells = <2>; 69*621d7d08SGuomin Chen 70*621d7d08SGuomin Chen mbox_ap2pm: mailbox@30000000 { 71*621d7d08SGuomin Chen compatible = "cix,sky1-mbox"; 72*621d7d08SGuomin Chen reg = <0 0x30000000 0 0x10000>; 73*621d7d08SGuomin Chen interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 74*621d7d08SGuomin Chen #mbox-cells = <1>; 75*621d7d08SGuomin Chen cix,mbox-dir = "tx"; 76*621d7d08SGuomin Chen }; 77*621d7d08SGuomin Chen }; 78