xref: /linux/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/brcm,iproc-pdc-mbox.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Broadcom iProc PDC mailbox
8
9maintainers:
10  - Ray Jui <rjui@broadcom.com>
11  - Scott Branden <sbranden@broadcom.com>
12
13description:
14  The PDC driver manages data transfer to and from various offload engines on
15  some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is one
16  device tree entry per block. On some chips, the PDC functionality is handled
17  by the FA2 (Northstar Plus).
18
19properties:
20  compatible:
21    enum:
22      - brcm,iproc-pdc-mbox
23      - brcm,iproc-fa2-mbox
24
25  reg:
26    maxItems: 1
27
28  dma-coherent: true
29
30  interrupts:
31    maxItems: 1
32
33  '#mbox-cells':
34    const: 1
35
36  brcm,rx-status-len:
37    description:
38      Length of metadata preceding received frames, in bytes.
39    $ref: /schemas/types.yaml#/definitions/uint32
40
41  brcm,use-bcm-hdr:
42    type: boolean
43    description:
44      Present if a BCM header precedes each frame.
45
46required:
47  - compatible
48  - reg
49  - interrupts
50  - '#mbox-cells'
51  - brcm,rx-status-len
52
53additionalProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/interrupt-controller/arm-gic.h>
58
59    mailbox0@612c0000 {
60        compatible = "brcm,iproc-pdc-mbox";
61        reg = <0x612c0000 0x445>;
62        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
63        #mbox-cells = <1>;
64        brcm,rx-status-len = <32>;
65        brcm,use-bcm-hdr;
66    };
67