1*a8689f65SFlorian VaussardOMAP2+ IOMMU 2*a8689f65SFlorian Vaussard 3*a8689f65SFlorian VaussardRequired properties: 4*a8689f65SFlorian Vaussard- compatible : Should be one of, 5*a8689f65SFlorian Vaussard "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances 6*a8689f65SFlorian Vaussard "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances 7*a8689f65SFlorian Vaussard "ti,dra7-iommu" for DRA7xx IOMMU instances 8*a8689f65SFlorian Vaussard- ti,hwmods : Name of the hwmod associated with the IOMMU instance 9*a8689f65SFlorian Vaussard- reg : Address space for the configuration registers 10*a8689f65SFlorian Vaussard- interrupts : Interrupt specifier for the IOMMU instance 11*a8689f65SFlorian Vaussard 12*a8689f65SFlorian VaussardOptional properties: 13*a8689f65SFlorian Vaussard- ti,#tlb-entries : Number of entries in the translation look-aside buffer. 14*a8689f65SFlorian Vaussard Should be either 8 or 32 (default: 32) 15*a8689f65SFlorian Vaussard- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing 16*a8689f65SFlorian Vaussard back a bus error response on MMU faults. 17*a8689f65SFlorian Vaussard 18*a8689f65SFlorian VaussardExample: 19*a8689f65SFlorian Vaussard /* OMAP3 ISP MMU */ 20*a8689f65SFlorian Vaussard mmu_isp: mmu@480bd400 { 21*a8689f65SFlorian Vaussard compatible = "ti,omap2-iommu"; 22*a8689f65SFlorian Vaussard reg = <0x480bd400 0x80>; 23*a8689f65SFlorian Vaussard interrupts = <24>; 24*a8689f65SFlorian Vaussard ti,hwmods = "mmu_isp"; 25*a8689f65SFlorian Vaussard ti,#tlb-entries = <8>; 26*a8689f65SFlorian Vaussard }; 27