1a8689f65SFlorian VaussardOMAP2+ IOMMU 2a8689f65SFlorian Vaussard 3a8689f65SFlorian VaussardRequired properties: 4a8689f65SFlorian Vaussard- compatible : Should be one of, 5a8689f65SFlorian Vaussard "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances 6a8689f65SFlorian Vaussard "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances 7a8689f65SFlorian Vaussard "ti,dra7-iommu" for DRA7xx IOMMU instances 8a8689f65SFlorian Vaussard- ti,hwmods : Name of the hwmod associated with the IOMMU instance 9a8689f65SFlorian Vaussard- reg : Address space for the configuration registers 10a8689f65SFlorian Vaussard- interrupts : Interrupt specifier for the IOMMU instance 11*a73622a7SSuman Anna- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, 12*a73622a7SSuman Anna and needs no additional data in the pargs specifier. Please 13*a73622a7SSuman Anna also refer to the generic bindings document for more info 14*a73622a7SSuman Anna on this property, 15*a73622a7SSuman Anna Documentation/devicetree/bindings/iommu/iommu.txt 16a8689f65SFlorian Vaussard 17a8689f65SFlorian VaussardOptional properties: 18a8689f65SFlorian Vaussard- ti,#tlb-entries : Number of entries in the translation look-aside buffer. 19a8689f65SFlorian Vaussard Should be either 8 or 32 (default: 32) 20a8689f65SFlorian Vaussard- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing 21a8689f65SFlorian Vaussard back a bus error response on MMU faults. 22a8689f65SFlorian Vaussard 23a8689f65SFlorian VaussardExample: 24a8689f65SFlorian Vaussard /* OMAP3 ISP MMU */ 25a8689f65SFlorian Vaussard mmu_isp: mmu@480bd400 { 26*a73622a7SSuman Anna #iommu-cells = <0>; 27a8689f65SFlorian Vaussard compatible = "ti,omap2-iommu"; 28a8689f65SFlorian Vaussard reg = <0x480bd400 0x80>; 29a8689f65SFlorian Vaussard interrupts = <24>; 30a8689f65SFlorian Vaussard ti,hwmods = "mmu_isp"; 31a8689f65SFlorian Vaussard ti,#tlb-entries = <8>; 32a8689f65SFlorian Vaussard }; 33