xref: /linux/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V IOMMU Architecture Implementation
8
9maintainers:
10  - Tomasz Jeznach <tjeznach@rivosinc.com>
11
12description: |
13  The RISC-V IOMMU provides memory address translation and isolation for
14  input and output devices, supporting per-device translation context,
15  shared process address spaces including the ATS and PRI components of
16  the PCIe specification, two stage address translation and MSI remapping.
17  It supports identical translation table format to the RISC-V address
18  translation tables with page level access and protection attributes.
19  Hardware uses in-memory command and fault reporting queues with wired
20  interrupt or MSI notifications.
21
22  Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
23
24  For information on assigning RISC-V IOMMU to its peripheral devices,
25  see generic IOMMU bindings.
26
27properties:
28  # For PCIe IOMMU hardware compatible property should contain the vendor
29  # and device ID according to the PCI Bus Binding specification.
30  # Since PCI provides built-in identification methods, compatible is not
31  # actually required. For non-PCIe hardware implementations 'riscv,iommu'
32  # should be specified along with 'reg' property providing MMIO location.
33  compatible:
34    oneOf:
35      - items:
36          - enum:
37              - qemu,riscv-iommu
38          - const: riscv,iommu
39      - items:
40          - enum:
41              - pci1efd,edf1
42          - const: riscv,pci-iommu
43
44  reg:
45    maxItems: 1
46    description:
47      For non-PCI devices this represents base address and size of for the
48      IOMMU memory mapped registers interface.
49      For PCI IOMMU hardware implementation this should represent an address
50      of the IOMMU, as defined in the PCI Bus Binding reference.
51
52  '#iommu-cells':
53    const: 1
54    description:
55      The single cell describes the requester id emitted by a master to the
56      IOMMU.
57
58  interrupts:
59    minItems: 1
60    maxItems: 4
61    description:
62      Wired interrupt vectors available for RISC-V IOMMU to notify the
63      RISC-V HARTS. The cause to interrupt vector is software defined
64      using IVEC IOMMU register.
65
66  msi-parent: true
67
68  power-domains:
69    maxItems: 1
70
71required:
72  - compatible
73  - reg
74  - '#iommu-cells'
75
76additionalProperties: false
77
78examples:
79  - |+
80    /* Example 1 (IOMMU device with wired interrupts) */
81    #include <dt-bindings/interrupt-controller/irq.h>
82
83    iommu1: iommu@1bccd000 {
84        compatible = "qemu,riscv-iommu", "riscv,iommu";
85        reg = <0x1bccd000 0x1000>;
86        interrupt-parent = <&aplic_smode>;
87        interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
88                     <33 IRQ_TYPE_LEVEL_HIGH>,
89                     <34 IRQ_TYPE_LEVEL_HIGH>,
90                     <35 IRQ_TYPE_LEVEL_HIGH>;
91        #iommu-cells = <1>;
92    };
93
94    /* Device with two IOMMU device IDs, 0 and 7 */
95    master1 {
96        iommus = <&iommu1 0>, <&iommu1 7>;
97    };
98
99  - |+
100    /* Example 2 (IOMMU device with shared wired interrupt) */
101    #include <dt-bindings/interrupt-controller/irq.h>
102
103    iommu2: iommu@1bccd000 {
104        compatible = "qemu,riscv-iommu", "riscv,iommu";
105        reg = <0x1bccd000 0x1000>;
106        interrupt-parent = <&aplic_smode>;
107        interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
108        #iommu-cells = <1>;
109    };
110
111  - |+
112    /* Example 3 (IOMMU device with MSIs) */
113    iommu3: iommu@1bcdd000 {
114        compatible = "qemu,riscv-iommu", "riscv,iommu";
115        reg = <0x1bccd000 0x1000>;
116        msi-parent = <&imsics_smode>;
117        #iommu-cells = <1>;
118    };
119
120  - |+
121    /* Example 4 (IOMMU PCIe device with MSIs) */
122    bus {
123        #address-cells = <2>;
124        #size-cells = <2>;
125
126        pcie@30000000 {
127            device_type = "pci";
128            #address-cells = <3>;
129            #size-cells = <2>;
130            reg = <0x0 0x30000000  0x0 0x1000000>;
131            ranges = <0x02000000 0x0 0x41000000  0x0 0x41000000  0x0 0x0f000000>;
132
133            /*
134             * The IOMMU manages all functions in this PCI domain except
135             * itself. Omit BDF 00:01.0.
136             */
137            iommu-map = <0x0 &iommu0 0x0 0x8>,
138                        <0x9 &iommu0 0x9 0xfff7>;
139
140            /* The IOMMU programming interface uses slot 00:01.0 */
141            iommu0: iommu@1,0 {
142               compatible = "pci1efd,edf1", "riscv,pci-iommu";
143               reg = <0x800 0 0 0 0>;
144               #iommu-cells = <1>;
145            };
146        };
147    };
148