xref: /linux/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VMSA-Compatible IOMMU
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12description:
13  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
14  It provides address translation for bus masters outside of the CPU, each
15  connected to the IPMMU through a port called micro-TLB.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
23              - renesas,ipmmu-r8a7742  # RZ/G1H
24              - renesas,ipmmu-r8a7743  # RZ/G1M
25              - renesas,ipmmu-r8a7744  # RZ/G1N
26              - renesas,ipmmu-r8a7745  # RZ/G1E
27              - renesas,ipmmu-r8a7790  # R-Car H2
28              - renesas,ipmmu-r8a7791  # R-Car M2-W
29              - renesas,ipmmu-r8a7793  # R-Car M2-N
30              - renesas,ipmmu-r8a7794  # R-Car E2
31          - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
32
33      - items:
34          - enum:
35              - renesas,ipmmu-r8a774a1 # RZ/G2M
36              - renesas,ipmmu-r8a774b1 # RZ/G2N
37              - renesas,ipmmu-r8a774c0 # RZ/G2E
38              - renesas,ipmmu-r8a774e1 # RZ/G2H
39              - renesas,ipmmu-r8a7795  # R-Car H3
40              - renesas,ipmmu-r8a7796  # R-Car M3-W
41              - renesas,ipmmu-r8a77961 # R-Car M3-W+
42              - renesas,ipmmu-r8a77965 # R-Car M3-N
43              - renesas,ipmmu-r8a77970 # R-Car V3M
44              - renesas,ipmmu-r8a77980 # R-Car V3H
45              - renesas,ipmmu-r8a77990 # R-Car E3
46              - renesas,ipmmu-r8a77995 # R-Car D3
47
48      - items:
49          - enum:
50              - renesas,ipmmu-r8a779a0           # R-Car V3U
51              - renesas,ipmmu-r8a779f0           # R-Car S4-8
52          - const: renesas,rcar-gen4-ipmmu-vmsa  # R-Car Gen4
53
54  reg:
55    maxItems: 1
56
57  interrupts:
58    minItems: 1
59    description:
60      Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
61    items:
62      - description: non-secure mode
63      - description: secure mode if supported
64
65  '#iommu-cells':
66    const: 1
67    description:
68      The number of the micro-TLB that the device is connected to.
69
70  power-domains:
71    maxItems: 1
72
73  renesas,ipmmu-main:
74    $ref: /schemas/types.yaml#/definitions/phandle-array
75    items:
76      - items:
77          - description: phandle to main IPMMU
78          - description: the interrupt bit number associated with the particular
79              cache IPMMU device. The interrupt bit number needs to match the main
80              IPMMU IMSSTR register. Only used by cache IPMMU instances.
81    description:
82      Reference to the main IPMMU phandle plus 1 cell. The cell is
83      the interrupt bit number associated with the particular cache IPMMU
84      device. The interrupt bit number needs to match the main IPMMU IMSSTR
85      register. Only used by cache IPMMU instances.
86
87required:
88  - compatible
89  - reg
90  - '#iommu-cells'
91
92oneOf:
93  - required:
94      - interrupts
95  - required:
96      - renesas,ipmmu-main
97
98additionalProperties: false
99
100allOf:
101  - if:
102      properties:
103        compatible:
104          not:
105            contains:
106              const: renesas,ipmmu-vmsa
107    then:
108      required:
109        - power-domains
110
111examples:
112  - |
113    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
114    #include <dt-bindings/interrupt-controller/arm-gic.h>
115    #include <dt-bindings/power/r8a7791-sysc.h>
116
117    ipmmu_mx: iommu@fe951000 {
118        compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
119        reg = <0xfe951000 0x1000>;
120        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
121                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
122        #iommu-cells = <1>;
123    };
124