xref: /linux/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml (revision 6e7fd890f1d6ac83805409e9c346240de2705584) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VMSA-Compatible IOMMU
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12description:
13  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
14  It provides address translation for bus masters outside of the CPU, each
15  connected to the IPMMU through a port called micro-TLB.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
23              - renesas,ipmmu-r8a7742  # RZ/G1H
24              - renesas,ipmmu-r8a7743  # RZ/G1M
25              - renesas,ipmmu-r8a7744  # RZ/G1N
26              - renesas,ipmmu-r8a7745  # RZ/G1E
27              - renesas,ipmmu-r8a7790  # R-Car H2
28              - renesas,ipmmu-r8a7791  # R-Car M2-W
29              - renesas,ipmmu-r8a7793  # R-Car M2-N
30              - renesas,ipmmu-r8a7794  # R-Car E2
31          - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
32
33      - items:
34          - enum:
35              - renesas,ipmmu-r8a774a1 # RZ/G2M
36              - renesas,ipmmu-r8a774b1 # RZ/G2N
37              - renesas,ipmmu-r8a774c0 # RZ/G2E
38              - renesas,ipmmu-r8a774e1 # RZ/G2H
39              - renesas,ipmmu-r8a7795  # R-Car H3
40              - renesas,ipmmu-r8a7796  # R-Car M3-W
41              - renesas,ipmmu-r8a77961 # R-Car M3-W+
42              - renesas,ipmmu-r8a77965 # R-Car M3-N
43              - renesas,ipmmu-r8a77970 # R-Car V3M
44              - renesas,ipmmu-r8a77980 # R-Car V3H
45              - renesas,ipmmu-r8a77990 # R-Car E3
46              - renesas,ipmmu-r8a77995 # R-Car D3
47
48      - items:
49          - enum:
50              - renesas,ipmmu-r8a779a0           # R-Car V3U
51              - renesas,ipmmu-r8a779f0           # R-Car S4-8
52              - renesas,ipmmu-r8a779g0           # R-Car V4H
53              - renesas,ipmmu-r8a779h0           # R-Car V4M
54          - const: renesas,rcar-gen4-ipmmu-vmsa  # R-Car Gen4
55
56  reg:
57    maxItems: 1
58
59  interrupts:
60    minItems: 1
61    description:
62      Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
63    items:
64      - description: non-secure mode
65      - description: secure mode if supported
66
67  '#iommu-cells':
68    const: 1
69    description:
70      The number of the micro-TLB that the device is connected to.
71
72  power-domains:
73    maxItems: 1
74
75  renesas,ipmmu-main:
76    $ref: /schemas/types.yaml#/definitions/phandle-array
77    items:
78      - minItems: 1
79        items:
80          - description: phandle to main IPMMU
81          - description:
82              The interrupt bit number associated with the particular cache
83              IPMMU device. If present, the interrupt bit number needs to match
84              the main IPMMU IMSSTR register. Only used by cache IPMMU
85              instances.
86    description:
87      Reference to the main IPMMU.
88
89required:
90  - compatible
91  - reg
92  - '#iommu-cells'
93
94oneOf:
95  - required:
96      - interrupts
97  - required:
98      - renesas,ipmmu-main
99
100additionalProperties: false
101
102allOf:
103  - if:
104      properties:
105        compatible:
106          not:
107            contains:
108              const: renesas,ipmmu-vmsa
109    then:
110      required:
111        - power-domains
112
113  - if:
114      properties:
115        compatible:
116          contains:
117            const: renesas,rcar-gen4-ipmmu-vmsa
118    then:
119      properties:
120        renesas,ipmmu-main:
121          items:
122            - maxItems: 1
123    else:
124      properties:
125        renesas,ipmmu-main:
126          items:
127            - minItems: 2
128
129examples:
130  - |
131    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
132    #include <dt-bindings/interrupt-controller/arm-gic.h>
133    #include <dt-bindings/power/r8a7791-sysc.h>
134
135    ipmmu_mx: iommu@fe951000 {
136        compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
137        reg = <0xfe951000 0x1000>;
138        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
139                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
140        #iommu-cells = <1>;
141    };
142