xref: /linux/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies legacy IOMMU implementations
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm "B" family devices which are not compatible with arm-smmu have
14  a similar looking IOMMU, but without access to the global register space
15  and optionally requiring additional configuration to route context IRQs
16  to non-secure vs secure interrupt line.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - qcom,msm8916-iommu
24              - qcom,msm8953-iommu
25          - const: qcom,msm-iommu-v1
26      - items:
27          - enum:
28              - qcom,msm8953-iommu
29              - qcom,msm8976-iommu
30          - const: qcom,msm-iommu-v2
31
32  clocks:
33    items:
34      - description: Clock required for IOMMU register group access
35      - description: Clock required for underlying bus access
36
37  clock-names:
38    items:
39      - const: iface
40      - const: bus
41
42  power-domains:
43    maxItems: 1
44
45  reg:
46    maxItems: 1
47
48  ranges: true
49
50  qcom,iommu-secure-id:
51    $ref: /schemas/types.yaml#/definitions/uint32
52    description:
53      The SCM secure ID of the IOMMU instance.
54
55  '#address-cells':
56    const: 1
57
58  '#size-cells':
59    const: 1
60
61  '#iommu-cells':
62    const: 1
63
64patternProperties:
65  "^iommu-ctx@[0-9a-f]+$":
66    type: object
67    additionalProperties: false
68    properties:
69      compatible:
70        enum:
71          - qcom,msm-iommu-v1-ns
72          - qcom,msm-iommu-v1-sec
73          - qcom,msm-iommu-v2-ns
74          - qcom,msm-iommu-v2-sec
75
76      interrupts:
77        maxItems: 1
78
79      reg:
80        maxItems: 1
81
82      qcom,ctx-asid:
83        $ref: /schemas/types.yaml#/definitions/uint32
84        description:
85          The ASID number associated to the context bank.
86
87    required:
88      - compatible
89      - interrupts
90      - reg
91
92required:
93  - compatible
94  - clocks
95  - clock-names
96  - ranges
97  - '#address-cells'
98  - '#size-cells'
99  - '#iommu-cells'
100
101additionalProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
106    #include <dt-bindings/interrupt-controller/arm-gic.h>
107
108    apps_iommu: iommu@1e20000 {
109      compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
110      reg = <0x01ef0000 0x3000>;
111      clocks = <&gcc GCC_SMMU_CFG_CLK>,
112               <&gcc GCC_APSS_TCU_CLK>;
113      clock-names = "iface", "bus";
114      qcom,iommu-secure-id = <17>;
115      #address-cells = <1>;
116      #size-cells = <1>;
117      #iommu-cells = <1>;
118      ranges = <0 0x01e20000 0x40000>;
119
120      /* mdp_0: */
121      iommu-ctx@4000 {
122        compatible = "qcom,msm-iommu-v1-ns";
123        reg = <0x4000 0x1000>;
124        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
125      };
126    };
127