1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - qcom,sm6375-smmu-v2 33 - const: qcom,smmu-v2 34 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 36 items: 37 - enum: 38 - qcom,qcm2290-smmu-500 39 - qcom,qcs615-smmu-500 40 - qcom,qcs8300-smmu-500 41 - qcom,qdu1000-smmu-500 42 - qcom,sa8255p-smmu-500 43 - qcom,sa8775p-smmu-500 44 - qcom,sar2130p-smmu-500 45 - qcom,sc7180-smmu-500 46 - qcom,sc7280-smmu-500 47 - qcom,sc8180x-smmu-500 48 - qcom,sc8280xp-smmu-500 49 - qcom,sdm670-smmu-500 50 - qcom,sdm845-smmu-500 51 - qcom,sdx55-smmu-500 52 - qcom,sdx65-smmu-500 53 - qcom,sdx75-smmu-500 54 - qcom,sm6115-smmu-500 55 - qcom,sm6125-smmu-500 56 - qcom,sm6350-smmu-500 57 - qcom,sm6375-smmu-500 58 - qcom,sm8150-smmu-500 59 - qcom,sm8250-smmu-500 60 - qcom,sm8350-smmu-500 61 - qcom,sm8450-smmu-500 62 - qcom,sm8550-smmu-500 63 - qcom,sm8650-smmu-500 64 - qcom,x1e80100-smmu-500 65 - const: qcom,smmu-500 66 - const: arm,mmu-500 67 68 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 69 deprecated: true 70 items: 71 # Do not add additional SoC to this list. Instead use two previous lists. 72 - enum: 73 - qcom,qcm2290-smmu-500 74 - qcom,sc7180-smmu-500 75 - qcom,sc7280-smmu-500 76 - qcom,sc8180x-smmu-500 77 - qcom,sc8280xp-smmu-500 78 - qcom,sdm845-smmu-500 79 - qcom,sm6115-smmu-500 80 - qcom,sm6350-smmu-500 81 - qcom,sm6375-smmu-500 82 - qcom,sm8150-smmu-500 83 - qcom,sm8250-smmu-500 84 - qcom,sm8350-smmu-500 85 - qcom,sm8450-smmu-500 86 - const: arm,mmu-500 87 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 88 items: 89 - enum: 90 - qcom,qcm2290-smmu-500 91 - qcom,sa8255p-smmu-500 92 - qcom,sa8775p-smmu-500 93 - qcom,sar2130p-smmu-500 94 - qcom,sc7280-smmu-500 95 - qcom,sc8180x-smmu-500 96 - qcom,sc8280xp-smmu-500 97 - qcom,sm6115-smmu-500 98 - qcom,sm6125-smmu-500 99 - qcom,sm8150-smmu-500 100 - qcom,sm8250-smmu-500 101 - qcom,sm8350-smmu-500 102 - qcom,sm8450-smmu-500 103 - qcom,sm8550-smmu-500 104 - qcom,sm8650-smmu-500 105 - qcom,x1e80100-smmu-500 106 - const: qcom,adreno-smmu 107 - const: qcom,smmu-500 108 - const: arm,mmu-500 109 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 110 deprecated: true 111 items: 112 # Do not add additional SoC to this list. Instead use previous list. 113 - enum: 114 - qcom,sc7280-smmu-500 115 - qcom,sm8150-smmu-500 116 - qcom,sm8250-smmu-500 117 - const: qcom,adreno-smmu 118 - const: arm,mmu-500 119 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 120 items: 121 - enum: 122 - qcom,msm8996-smmu-v2 123 - qcom,sc7180-smmu-v2 124 - qcom,sdm630-smmu-v2 125 - qcom,sdm845-smmu-v2 126 - qcom,sm6350-smmu-v2 127 - qcom,sm7150-smmu-v2 128 - const: qcom,adreno-smmu 129 - const: qcom,smmu-v2 130 - description: Qcom Adreno GPUs on Google Cheza platform 131 items: 132 - const: qcom,sdm845-smmu-v2 133 - const: qcom,smmu-v2 134 - description: Marvell SoCs implementing "arm,mmu-500" 135 items: 136 - const: marvell,ap806-smmu-500 137 - const: arm,mmu-500 138 - description: NVIDIA SoCs that require memory controller interaction 139 and may program multiple ARM MMU-500s identically with the memory 140 controller interleaving translations between multiple instances 141 for improved performance. 142 items: 143 - enum: 144 - nvidia,tegra186-smmu 145 - nvidia,tegra194-smmu 146 - nvidia,tegra234-smmu 147 - const: nvidia,smmu-500 148 - items: 149 - const: arm,mmu-500 150 - const: arm,smmu-v2 151 - items: 152 - enum: 153 - arm,mmu-400 154 - arm,mmu-401 155 - const: arm,smmu-v1 156 - enum: 157 - arm,smmu-v1 158 - arm,smmu-v2 159 - arm,mmu-400 160 - arm,mmu-401 161 - arm,mmu-500 162 - cavium,smmu-v2 163 164 reg: 165 minItems: 1 166 maxItems: 2 167 168 '#global-interrupts': 169 description: The number of global interrupts exposed by the device. 170 $ref: /schemas/types.yaml#/definitions/uint32 171 minimum: 0 172 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 173 174 '#iommu-cells': 175 enum: [ 1, 2 ] 176 description: | 177 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 178 value of 1, each IOMMU specifier represents a distinct stream ID emitted 179 by that device into the relevant SMMU. 180 181 SMMUs with stream matching support and complex masters may use a value of 182 2, where the second cell of the IOMMU specifier represents an SMR mask to 183 combine with the ID in the first cell. Care must be taken to ensure the 184 set of matched IDs does not result in conflicts. 185 186 interrupts: 187 minItems: 1 188 maxItems: 388 # 260 plus 128 contexts 189 description: | 190 Interrupt list, with the first #global-interrupts entries corresponding to 191 the global interrupts and any following entries corresponding to context 192 interrupts, specified in order of their indexing by the SMMU. 193 194 For SMMUv2 implementations, there must be exactly one interrupt per 195 context bank. In the case of a single, combined interrupt, it must be 196 listed multiple times. 197 198 dma-coherent: 199 description: | 200 Present if page table walks made by the SMMU are cache coherent with the 201 CPU. 202 203 NOTE: this only applies to the SMMU itself, not masters connected 204 upstream of the SMMU. 205 206 calxeda,smmu-secure-config-access: 207 type: boolean 208 description: 209 Enable proper handling of buggy implementations that always use secure 210 access to SMMU configuration registers. In this case non-secure aliases of 211 secure registers have to be used during SMMU configuration. 212 213 stream-match-mask: 214 $ref: /schemas/types.yaml#/definitions/uint32 215 description: | 216 For SMMUs supporting stream matching and using #iommu-cells = <1>, 217 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 218 be programmed into the SMRn.MASK field of every stream match register 219 used). For cases where it is desirable to ignore some portion of every 220 Stream ID (e.g. for certain MMU-500 configurations given globally unique 221 input IDs). This property is not valid for SMMUs using stream indexing, or 222 using stream matching with #iommu-cells = <2>, and may be ignored if 223 present in such cases. 224 225 clock-names: 226 minItems: 1 227 maxItems: 7 228 229 clocks: 230 minItems: 1 231 maxItems: 7 232 233 power-domains: 234 minItems: 1 235 maxItems: 3 236 237 nvidia,memory-controller: 238 description: | 239 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 240 The memory controller needs to be programmed with a mapping of memory 241 client IDs to ARM SMMU stream IDs. 242 243 If this property is absent, the mapping programmed by early firmware 244 will be used and it is not guaranteed that IOMMU translations will be 245 enabled for any given device. 246 $ref: /schemas/types.yaml#/definitions/phandle 247 248required: 249 - compatible 250 - reg 251 - '#global-interrupts' 252 - '#iommu-cells' 253 - interrupts 254 255additionalProperties: false 256 257allOf: 258 - if: 259 properties: 260 compatible: 261 contains: 262 enum: 263 - nvidia,tegra186-smmu 264 - nvidia,tegra194-smmu 265 - nvidia,tegra234-smmu 266 then: 267 properties: 268 reg: 269 minItems: 1 270 maxItems: 2 271 272 # The reference to the memory controller is required to ensure that the 273 # memory client to stream ID mapping can be done synchronously with the 274 # IOMMU attachment. 275 required: 276 - nvidia,memory-controller 277 else: 278 properties: 279 reg: 280 maxItems: 1 281 282 - if: 283 properties: 284 compatible: 285 contains: 286 enum: 287 - qcom,msm8998-smmu-v2 288 - qcom,sdm630-smmu-v2 289 then: 290 anyOf: 291 - properties: 292 clock-names: 293 items: 294 - const: bus 295 clocks: 296 items: 297 - description: bus clock required for downstream bus access and for 298 the smmu ptw 299 - properties: 300 clock-names: 301 items: 302 - const: iface 303 - const: mem 304 - const: mem_iface 305 clocks: 306 items: 307 - description: interface clock required to access smmu's registers 308 through the TCU's programming interface. 309 - description: bus clock required for memory access 310 - description: bus clock required for GPU memory access 311 - properties: 312 clock-names: 313 items: 314 - const: iface-mm 315 - const: iface-smmu 316 - const: bus-smmu 317 clocks: 318 items: 319 - description: interface clock required to access mnoc's registers 320 through the TCU's programming interface. 321 - description: interface clock required to access smmu's registers 322 through the TCU's programming interface. 323 - description: bus clock required for the smmu ptw 324 325 - if: 326 properties: 327 compatible: 328 contains: 329 enum: 330 - qcom,sm6375-smmu-v2 331 then: 332 anyOf: 333 - properties: 334 clock-names: 335 items: 336 - const: bus 337 clocks: 338 items: 339 - description: bus clock required for downstream bus access and for 340 the smmu ptw 341 - properties: 342 clock-names: 343 items: 344 - const: iface 345 - const: mem 346 - const: mem_iface 347 clocks: 348 items: 349 - description: interface clock required to access smmu's registers 350 through the TCU's programming interface. 351 - description: bus clock required for memory access 352 - description: bus clock required for GPU memory access 353 - properties: 354 clock-names: 355 items: 356 - const: iface-mm 357 - const: iface-smmu 358 - const: bus-mm 359 - const: bus-smmu 360 clocks: 361 items: 362 - description: interface clock required to access mnoc's registers 363 through the TCU's programming interface. 364 - description: interface clock required to access smmu's registers 365 through the TCU's programming interface. 366 - description: bus clock required for downstream bus access 367 - description: bus clock required for the smmu ptw 368 369 - if: 370 properties: 371 compatible: 372 contains: 373 enum: 374 - qcom,msm8996-smmu-v2 375 - qcom,sc7180-smmu-v2 376 - qcom,sdm845-smmu-v2 377 then: 378 properties: 379 clock-names: 380 items: 381 - const: bus 382 - const: iface 383 384 clocks: 385 items: 386 - description: bus clock required for downstream bus access and for 387 the smmu ptw 388 - description: interface clock required to access smmu's registers 389 through the TCU's programming interface. 390 391 - if: 392 properties: 393 compatible: 394 contains: 395 enum: 396 - qcom,sa8775p-smmu-500 397 - qcom,sc7280-smmu-500 398 - qcom,sc8280xp-smmu-500 399 then: 400 properties: 401 clock-names: 402 items: 403 - const: gcc_gpu_memnoc_gfx_clk 404 - const: gcc_gpu_snoc_dvm_gfx_clk 405 - const: gpu_cc_ahb_clk 406 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 407 - const: gpu_cc_cx_gmu_clk 408 - const: gpu_cc_hub_cx_int_clk 409 - const: gpu_cc_hub_aon_clk 410 411 clocks: 412 items: 413 - description: GPU memnoc_gfx clock 414 - description: GPU snoc_dvm_gfx clock 415 - description: GPU ahb clock 416 - description: GPU hlos1_vote_GPU smmu clock 417 - description: GPU cx_gmu clock 418 - description: GPU hub_cx_int clock 419 - description: GPU hub_aon clock 420 421 - if: 422 properties: 423 compatible: 424 contains: 425 enum: 426 - qcom,sc8180x-smmu-500 427 - qcom,sm6350-smmu-v2 428 - qcom,sm7150-smmu-v2 429 - qcom,sm8150-smmu-500 430 - qcom,sm8250-smmu-500 431 then: 432 properties: 433 clock-names: 434 items: 435 - const: ahb 436 - const: bus 437 - const: iface 438 439 clocks: 440 items: 441 - description: bus clock required for AHB bus access 442 - description: bus clock required for downstream bus access and for 443 the smmu ptw 444 - description: interface clock required to access smmu's registers 445 through the TCU's programming interface. 446 447 - if: 448 properties: 449 compatible: 450 items: 451 - enum: 452 - qcom,sm8350-smmu-500 453 - const: qcom,adreno-smmu 454 - const: qcom,smmu-500 455 - const: arm,mmu-500 456 then: 457 properties: 458 clock-names: 459 items: 460 - const: bus 461 - const: iface 462 - const: ahb 463 - const: hlos1_vote_gpu_smmu 464 - const: cx_gmu 465 - const: hub_cx_int 466 - const: hub_aon 467 clocks: 468 minItems: 7 469 maxItems: 7 470 471 - if: 472 properties: 473 compatible: 474 items: 475 - enum: 476 - qcom,qcm2290-smmu-500 477 - qcom,sm6115-smmu-500 478 - qcom,sm6125-smmu-500 479 - const: qcom,adreno-smmu 480 - const: qcom,smmu-500 481 - const: arm,mmu-500 482 then: 483 properties: 484 clock-names: 485 items: 486 - const: mem 487 - const: hlos 488 - const: iface 489 490 clocks: 491 items: 492 - description: GPU memory bus clock 493 - description: Voter clock required for HLOS SMMU access 494 - description: Interface clock required for register access 495 496 - if: 497 properties: 498 compatible: 499 items: 500 - const: qcom,sm8450-smmu-500 501 - const: qcom,adreno-smmu 502 - const: qcom,smmu-500 503 - const: arm,mmu-500 504 505 then: 506 properties: 507 clock-names: 508 items: 509 - const: gmu 510 - const: hub 511 - const: hlos 512 - const: bus 513 - const: iface 514 - const: ahb 515 516 clocks: 517 items: 518 - description: GMU clock 519 - description: GPU HUB clock 520 - description: HLOS vote clock 521 - description: GPU memory bus clock 522 - description: GPU SNoC bus clock 523 - description: GPU AHB clock 524 525 - if: 526 properties: 527 compatible: 528 items: 529 - enum: 530 - qcom,sar2130p-smmu-500 531 - qcom,sm8550-smmu-500 532 - qcom,sm8650-smmu-500 533 - qcom,x1e80100-smmu-500 534 - const: qcom,adreno-smmu 535 - const: qcom,smmu-500 536 - const: arm,mmu-500 537 then: 538 properties: 539 clock-names: 540 items: 541 - const: hlos 542 - const: bus 543 - const: iface 544 - const: ahb 545 546 clocks: 547 items: 548 - description: HLOS vote clock 549 - description: GPU memory bus clock 550 - description: GPU SNoC bus clock 551 - description: GPU AHB clock 552 553 # Disallow clocks for all other platforms with specific compatibles 554 - if: 555 properties: 556 compatible: 557 contains: 558 enum: 559 - cavium,smmu-v2 560 - marvell,ap806-smmu-500 561 - nvidia,smmu-500 562 - qcom,qcs615-smmu-500 563 - qcom,qcs8300-smmu-500 564 - qcom,qdu1000-smmu-500 565 - qcom,sa8255p-smmu-500 566 - qcom,sc7180-smmu-500 567 - qcom,sdm670-smmu-500 568 - qcom,sdm845-smmu-500 569 - qcom,sdx55-smmu-500 570 - qcom,sdx65-smmu-500 571 - qcom,sm6350-smmu-500 572 - qcom,sm6375-smmu-500 573 then: 574 properties: 575 clock-names: false 576 clocks: false 577 578 - if: 579 properties: 580 compatible: 581 contains: 582 const: qcom,sm6375-smmu-500 583 then: 584 properties: 585 power-domains: 586 items: 587 - description: SNoC MMU TBU RT GDSC 588 - description: SNoC MMU TBU NRT GDSC 589 - description: SNoC TURING MMU TBU0 GDSC 590 591 required: 592 - power-domains 593 else: 594 properties: 595 power-domains: 596 maxItems: 1 597 598examples: 599 - |+ 600 /* SMMU with stream matching or stream indexing */ 601 smmu1: iommu@ba5e0000 { 602 compatible = "arm,smmu-v1"; 603 reg = <0xba5e0000 0x10000>; 604 #global-interrupts = <2>; 605 interrupts = <0 32 4>, 606 <0 33 4>, 607 <0 34 4>, /* This is the first context interrupt */ 608 <0 35 4>, 609 <0 36 4>, 610 <0 37 4>; 611 #iommu-cells = <1>; 612 }; 613 614 /* device with two stream IDs, 0 and 7 */ 615 master1 { 616 iommus = <&smmu1 0>, 617 <&smmu1 7>; 618 }; 619 620 621 /* SMMU with stream matching */ 622 smmu2: iommu@ba5f0000 { 623 compatible = "arm,smmu-v1"; 624 reg = <0xba5f0000 0x10000>; 625 #global-interrupts = <2>; 626 interrupts = <0 38 4>, 627 <0 39 4>, 628 <0 40 4>, /* This is the first context interrupt */ 629 <0 41 4>, 630 <0 42 4>, 631 <0 43 4>; 632 #iommu-cells = <2>; 633 }; 634 635 /* device with stream IDs 0 and 7 */ 636 master2 { 637 iommus = <&smmu2 0 0>, 638 <&smmu2 7 0>; 639 }; 640 641 /* device with stream IDs 1, 17, 33 and 49 */ 642 master3 { 643 iommus = <&smmu2 1 0x30>; 644 }; 645 646 647 /* ARM MMU-500 with 10-bit stream ID input configuration */ 648 smmu3: iommu@ba600000 { 649 compatible = "arm,mmu-500", "arm,smmu-v2"; 650 reg = <0xba600000 0x10000>; 651 #global-interrupts = <2>; 652 interrupts = <0 44 4>, 653 <0 45 4>, 654 <0 46 4>, /* This is the first context interrupt */ 655 <0 47 4>, 656 <0 48 4>, 657 <0 49 4>; 658 #iommu-cells = <1>; 659 /* always ignore appended 5-bit TBU number */ 660 stream-match-mask = <0x7c00>; 661 }; 662 663 bus { 664 /* bus whose child devices emit one unique 10-bit stream 665 ID each, but may master through multiple SMMU TBUs */ 666 iommu-map = <0 &smmu3 0 0x400>; 667 668 669 }; 670 671 - |+ 672 /* Qcom's arm,smmu-v2 implementation */ 673 #include <dt-bindings/interrupt-controller/arm-gic.h> 674 #include <dt-bindings/interrupt-controller/irq.h> 675 smmu4: iommu@d00000 { 676 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 677 reg = <0xd00000 0x10000>; 678 679 #global-interrupts = <1>; 680 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 683 #iommu-cells = <1>; 684 power-domains = <&mmcc 0>; 685 686 clocks = <&mmcc 123>, 687 <&mmcc 124>; 688 clock-names = "bus", "iface"; 689 }; 690