1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - const: qcom,smmu-v2 33 34 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 35 items: 36 - enum: 37 - qcom,qcm2290-smmu-500 38 - qcom,qdu1000-smmu-500 39 - qcom,sa8775p-smmu-500 40 - qcom,sc7180-smmu-500 41 - qcom,sc7280-smmu-500 42 - qcom,sc8180x-smmu-500 43 - qcom,sc8280xp-smmu-500 44 - qcom,sdm670-smmu-500 45 - qcom,sdm845-smmu-500 46 - qcom,sdx55-smmu-500 47 - qcom,sdx65-smmu-500 48 - qcom,sm6115-smmu-500 49 - qcom,sm6125-smmu-500 50 - qcom,sm6350-smmu-500 51 - qcom,sm6375-smmu-500 52 - qcom,sm8150-smmu-500 53 - qcom,sm8250-smmu-500 54 - qcom,sm8350-smmu-500 55 - qcom,sm8450-smmu-500 56 - const: qcom,smmu-500 57 - const: arm,mmu-500 58 59 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 60 deprecated: true 61 items: 62 # Do not add additional SoC to this list. Instead use two previous lists. 63 - enum: 64 - qcom,qcm2290-smmu-500 65 - qcom,sc7180-smmu-500 66 - qcom,sc7280-smmu-500 67 - qcom,sc8180x-smmu-500 68 - qcom,sc8280xp-smmu-500 69 - qcom,sdm845-smmu-500 70 - qcom,sm6115-smmu-500 71 - qcom,sm6350-smmu-500 72 - qcom,sm6375-smmu-500 73 - qcom,sm8150-smmu-500 74 - qcom,sm8250-smmu-500 75 - qcom,sm8350-smmu-500 76 - qcom,sm8450-smmu-500 77 - const: arm,mmu-500 78 79 - description: Qcom Adreno GPUs implementing "arm,smmu-500" 80 items: 81 - enum: 82 - qcom,sc7280-smmu-500 83 - qcom,sm8150-smmu-500 84 - qcom,sm8250-smmu-500 85 - const: qcom,adreno-smmu 86 - const: arm,mmu-500 87 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 88 items: 89 - enum: 90 - qcom,msm8996-smmu-v2 91 - qcom,sc7180-smmu-v2 92 - qcom,sdm630-smmu-v2 93 - qcom,sdm845-smmu-v2 94 - qcom,sm6350-smmu-v2 95 - const: qcom,adreno-smmu 96 - const: qcom,smmu-v2 97 - description: Qcom Adreno GPUs on Google Cheza platform 98 items: 99 - const: qcom,sdm845-smmu-v2 100 - const: qcom,smmu-v2 101 - description: Marvell SoCs implementing "arm,mmu-500" 102 items: 103 - const: marvell,ap806-smmu-500 104 - const: arm,mmu-500 105 - description: NVIDIA SoCs that require memory controller interaction 106 and may program multiple ARM MMU-500s identically with the memory 107 controller interleaving translations between multiple instances 108 for improved performance. 109 items: 110 - enum: 111 - nvidia,tegra186-smmu 112 - nvidia,tegra194-smmu 113 - nvidia,tegra234-smmu 114 - const: nvidia,smmu-500 115 - items: 116 - const: arm,mmu-500 117 - const: arm,smmu-v2 118 - items: 119 - enum: 120 - arm,mmu-400 121 - arm,mmu-401 122 - const: arm,smmu-v1 123 - enum: 124 - arm,smmu-v1 125 - arm,smmu-v2 126 - arm,mmu-400 127 - arm,mmu-401 128 - arm,mmu-500 129 - cavium,smmu-v2 130 131 reg: 132 minItems: 1 133 maxItems: 2 134 135 '#global-interrupts': 136 description: The number of global interrupts exposed by the device. 137 $ref: /schemas/types.yaml#/definitions/uint32 138 minimum: 0 139 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 140 141 '#iommu-cells': 142 enum: [ 1, 2 ] 143 description: | 144 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 145 value of 1, each IOMMU specifier represents a distinct stream ID emitted 146 by that device into the relevant SMMU. 147 148 SMMUs with stream matching support and complex masters may use a value of 149 2, where the second cell of the IOMMU specifier represents an SMR mask to 150 combine with the ID in the first cell. Care must be taken to ensure the 151 set of matched IDs does not result in conflicts. 152 153 interrupts: 154 minItems: 1 155 maxItems: 388 # 260 plus 128 contexts 156 description: | 157 Interrupt list, with the first #global-interrupts entries corresponding to 158 the global interrupts and any following entries corresponding to context 159 interrupts, specified in order of their indexing by the SMMU. 160 161 For SMMUv2 implementations, there must be exactly one interrupt per 162 context bank. In the case of a single, combined interrupt, it must be 163 listed multiple times. 164 165 dma-coherent: 166 description: | 167 Present if page table walks made by the SMMU are cache coherent with the 168 CPU. 169 170 NOTE: this only applies to the SMMU itself, not masters connected 171 upstream of the SMMU. 172 173 calxeda,smmu-secure-config-access: 174 type: boolean 175 description: 176 Enable proper handling of buggy implementations that always use secure 177 access to SMMU configuration registers. In this case non-secure aliases of 178 secure registers have to be used during SMMU configuration. 179 180 stream-match-mask: 181 $ref: /schemas/types.yaml#/definitions/uint32 182 description: | 183 For SMMUs supporting stream matching and using #iommu-cells = <1>, 184 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 185 be programmed into the SMRn.MASK field of every stream match register 186 used). For cases where it is desirable to ignore some portion of every 187 Stream ID (e.g. for certain MMU-500 configurations given globally unique 188 input IDs). This property is not valid for SMMUs using stream indexing, or 189 using stream matching with #iommu-cells = <2>, and may be ignored if 190 present in such cases. 191 192 clock-names: 193 minItems: 1 194 maxItems: 7 195 196 clocks: 197 minItems: 1 198 maxItems: 7 199 200 power-domains: 201 minItems: 1 202 maxItems: 3 203 204 nvidia,memory-controller: 205 description: | 206 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 207 The memory controller needs to be programmed with a mapping of memory 208 client IDs to ARM SMMU stream IDs. 209 210 If this property is absent, the mapping programmed by early firmware 211 will be used and it is not guaranteed that IOMMU translations will be 212 enabled for any given device. 213 $ref: /schemas/types.yaml#/definitions/phandle 214 215required: 216 - compatible 217 - reg 218 - '#global-interrupts' 219 - '#iommu-cells' 220 - interrupts 221 222additionalProperties: false 223 224allOf: 225 - if: 226 properties: 227 compatible: 228 contains: 229 enum: 230 - nvidia,tegra186-smmu 231 - nvidia,tegra194-smmu 232 - nvidia,tegra234-smmu 233 then: 234 properties: 235 reg: 236 minItems: 1 237 maxItems: 2 238 239 # The reference to the memory controller is required to ensure that the 240 # memory client to stream ID mapping can be done synchronously with the 241 # IOMMU attachment. 242 required: 243 - nvidia,memory-controller 244 else: 245 properties: 246 reg: 247 maxItems: 1 248 249 - if: 250 properties: 251 compatible: 252 contains: 253 enum: 254 - qcom,msm8998-smmu-v2 255 - qcom,sdm630-smmu-v2 256 then: 257 anyOf: 258 - properties: 259 clock-names: 260 items: 261 - const: bus 262 clocks: 263 items: 264 - description: bus clock required for downstream bus access and for 265 the smmu ptw 266 - properties: 267 clock-names: 268 items: 269 - const: iface 270 - const: mem 271 - const: mem_iface 272 clocks: 273 items: 274 - description: interface clock required to access smmu's registers 275 through the TCU's programming interface. 276 - description: bus clock required for memory access 277 - description: bus clock required for GPU memory access 278 - properties: 279 clock-names: 280 items: 281 - const: iface-mm 282 - const: iface-smmu 283 - const: bus-mm 284 - const: bus-smmu 285 clocks: 286 items: 287 - description: interface clock required to access mnoc's registers 288 through the TCU's programming interface. 289 - description: interface clock required to access smmu's registers 290 through the TCU's programming interface. 291 - description: bus clock required for downstream bus access 292 - description: bus clock required for the smmu ptw 293 294 - if: 295 properties: 296 compatible: 297 contains: 298 enum: 299 - qcom,msm8996-smmu-v2 300 - qcom,sc7180-smmu-v2 301 - qcom,sdm845-smmu-v2 302 then: 303 properties: 304 clock-names: 305 items: 306 - const: bus 307 - const: iface 308 309 clocks: 310 items: 311 - description: bus clock required for downstream bus access and for 312 the smmu ptw 313 - description: interface clock required to access smmu's registers 314 through the TCU's programming interface. 315 316 - if: 317 properties: 318 compatible: 319 contains: 320 const: qcom,sc7280-smmu-500 321 then: 322 properties: 323 clock-names: 324 items: 325 - const: gcc_gpu_memnoc_gfx_clk 326 - const: gcc_gpu_snoc_dvm_gfx_clk 327 - const: gpu_cc_ahb_clk 328 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 329 - const: gpu_cc_cx_gmu_clk 330 - const: gpu_cc_hub_cx_int_clk 331 - const: gpu_cc_hub_aon_clk 332 333 clocks: 334 items: 335 - description: GPU memnoc_gfx clock 336 - description: GPU snoc_dvm_gfx clock 337 - description: GPU ahb clock 338 - description: GPU hlos1_vote_GPU smmu clock 339 - description: GPU cx_gmu clock 340 - description: GPU hub_cx_int clock 341 - description: GPU hub_aon clock 342 343 - if: 344 properties: 345 compatible: 346 contains: 347 enum: 348 - qcom,sm6350-smmu-v2 349 - qcom,sm8150-smmu-500 350 - qcom,sm8250-smmu-500 351 then: 352 properties: 353 clock-names: 354 items: 355 - const: ahb 356 - const: bus 357 - const: iface 358 359 clocks: 360 items: 361 - description: bus clock required for AHB bus access 362 - description: bus clock required for downstream bus access and for 363 the smmu ptw 364 - description: interface clock required to access smmu's registers 365 through the TCU's programming interface. 366 367 # Disallow clocks for all other platforms with specific compatibles 368 - if: 369 properties: 370 compatible: 371 contains: 372 enum: 373 - cavium,smmu-v2 374 - marvell,ap806-smmu-500 375 - nvidia,smmu-500 376 - qcom,qcm2290-smmu-500 377 - qcom,qdu1000-smmu-500 378 - qcom,sa8775p-smmu-500 379 - qcom,sc7180-smmu-500 380 - qcom,sc8180x-smmu-500 381 - qcom,sc8280xp-smmu-500 382 - qcom,sdm670-smmu-500 383 - qcom,sdm845-smmu-500 384 - qcom,sdx55-smmu-500 385 - qcom,sdx65-smmu-500 386 - qcom,sm6115-smmu-500 387 - qcom,sm6125-smmu-500 388 - qcom,sm6350-smmu-500 389 - qcom,sm6375-smmu-500 390 - qcom,sm8350-smmu-500 391 - qcom,sm8450-smmu-500 392 then: 393 properties: 394 clock-names: false 395 clocks: false 396 397 - if: 398 properties: 399 compatible: 400 contains: 401 const: qcom,sm6375-smmu-500 402 then: 403 properties: 404 power-domains: 405 items: 406 - description: SNoC MMU TBU RT GDSC 407 - description: SNoC MMU TBU NRT GDSC 408 - description: SNoC TURING MMU TBU0 GDSC 409 410 required: 411 - power-domains 412 else: 413 properties: 414 power-domains: 415 maxItems: 1 416 417examples: 418 - |+ 419 /* SMMU with stream matching or stream indexing */ 420 smmu1: iommu@ba5e0000 { 421 compatible = "arm,smmu-v1"; 422 reg = <0xba5e0000 0x10000>; 423 #global-interrupts = <2>; 424 interrupts = <0 32 4>, 425 <0 33 4>, 426 <0 34 4>, /* This is the first context interrupt */ 427 <0 35 4>, 428 <0 36 4>, 429 <0 37 4>; 430 #iommu-cells = <1>; 431 }; 432 433 /* device with two stream IDs, 0 and 7 */ 434 master1 { 435 iommus = <&smmu1 0>, 436 <&smmu1 7>; 437 }; 438 439 440 /* SMMU with stream matching */ 441 smmu2: iommu@ba5f0000 { 442 compatible = "arm,smmu-v1"; 443 reg = <0xba5f0000 0x10000>; 444 #global-interrupts = <2>; 445 interrupts = <0 38 4>, 446 <0 39 4>, 447 <0 40 4>, /* This is the first context interrupt */ 448 <0 41 4>, 449 <0 42 4>, 450 <0 43 4>; 451 #iommu-cells = <2>; 452 }; 453 454 /* device with stream IDs 0 and 7 */ 455 master2 { 456 iommus = <&smmu2 0 0>, 457 <&smmu2 7 0>; 458 }; 459 460 /* device with stream IDs 1, 17, 33 and 49 */ 461 master3 { 462 iommus = <&smmu2 1 0x30>; 463 }; 464 465 466 /* ARM MMU-500 with 10-bit stream ID input configuration */ 467 smmu3: iommu@ba600000 { 468 compatible = "arm,mmu-500", "arm,smmu-v2"; 469 reg = <0xba600000 0x10000>; 470 #global-interrupts = <2>; 471 interrupts = <0 44 4>, 472 <0 45 4>, 473 <0 46 4>, /* This is the first context interrupt */ 474 <0 47 4>, 475 <0 48 4>, 476 <0 49 4>; 477 #iommu-cells = <1>; 478 /* always ignore appended 5-bit TBU number */ 479 stream-match-mask = <0x7c00>; 480 }; 481 482 bus { 483 /* bus whose child devices emit one unique 10-bit stream 484 ID each, but may master through multiple SMMU TBUs */ 485 iommu-map = <0 &smmu3 0 0x400>; 486 487 488 }; 489 490 - |+ 491 /* Qcom's arm,smmu-v2 implementation */ 492 #include <dt-bindings/interrupt-controller/arm-gic.h> 493 #include <dt-bindings/interrupt-controller/irq.h> 494 smmu4: iommu@d00000 { 495 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 496 reg = <0xd00000 0x10000>; 497 498 #global-interrupts = <1>; 499 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 502 #iommu-cells = <1>; 503 power-domains = <&mmcc 0>; 504 505 clocks = <&mmcc 123>, 506 <&mmcc 124>; 507 clock-names = "bus", "iface"; 508 }; 509