1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - qcom,sm6375-smmu-v2 33 - const: qcom,smmu-v2 34 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 36 items: 37 - enum: 38 - qcom,qcm2290-smmu-500 39 - qcom,qcs615-smmu-500 40 - qcom,qcs8300-smmu-500 41 - qcom,qdu1000-smmu-500 42 - qcom,sa8255p-smmu-500 43 - qcom,sa8775p-smmu-500 44 - qcom,sar2130p-smmu-500 45 - qcom,sc7180-smmu-500 46 - qcom,sc7280-smmu-500 47 - qcom,sc8180x-smmu-500 48 - qcom,sc8280xp-smmu-500 49 - qcom,sdm670-smmu-500 50 - qcom,sdm845-smmu-500 51 - qcom,sdx55-smmu-500 52 - qcom,sdx65-smmu-500 53 - qcom,sdx75-smmu-500 54 - qcom,sm6115-smmu-500 55 - qcom,sm6125-smmu-500 56 - qcom,sm6350-smmu-500 57 - qcom,sm6375-smmu-500 58 - qcom,sm8150-smmu-500 59 - qcom,sm8250-smmu-500 60 - qcom,sm8350-smmu-500 61 - qcom,sm8450-smmu-500 62 - qcom,sm8550-smmu-500 63 - qcom,sm8650-smmu-500 64 - qcom,sm8750-smmu-500 65 - qcom,x1e80100-smmu-500 66 - const: qcom,smmu-500 67 - const: arm,mmu-500 68 69 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 70 deprecated: true 71 items: 72 # Do not add additional SoC to this list. Instead use two previous lists. 73 - enum: 74 - qcom,qcm2290-smmu-500 75 - qcom,sc7180-smmu-500 76 - qcom,sc7280-smmu-500 77 - qcom,sc8180x-smmu-500 78 - qcom,sc8280xp-smmu-500 79 - qcom,sdm845-smmu-500 80 - qcom,sm6115-smmu-500 81 - qcom,sm6350-smmu-500 82 - qcom,sm6375-smmu-500 83 - qcom,sm8150-smmu-500 84 - qcom,sm8250-smmu-500 85 - qcom,sm8350-smmu-500 86 - qcom,sm8450-smmu-500 87 - const: arm,mmu-500 88 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 89 items: 90 - enum: 91 - qcom,qcm2290-smmu-500 92 - qcom,qcs615-smmu-500 93 - qcom,qcs8300-smmu-500 94 - qcom,sa8255p-smmu-500 95 - qcom,sa8775p-smmu-500 96 - qcom,sar2130p-smmu-500 97 - qcom,sc7280-smmu-500 98 - qcom,sc8180x-smmu-500 99 - qcom,sc8280xp-smmu-500 100 - qcom,sm6115-smmu-500 101 - qcom,sm6125-smmu-500 102 - qcom,sm8150-smmu-500 103 - qcom,sm8250-smmu-500 104 - qcom,sm8350-smmu-500 105 - qcom,sm8450-smmu-500 106 - qcom,sm8550-smmu-500 107 - qcom,sm8650-smmu-500 108 - qcom,sm8750-smmu-500 109 - qcom,x1e80100-smmu-500 110 - const: qcom,adreno-smmu 111 - const: qcom,smmu-500 112 - const: arm,mmu-500 113 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 114 deprecated: true 115 items: 116 # Do not add additional SoC to this list. Instead use previous list. 117 - enum: 118 - qcom,sc7280-smmu-500 119 - qcom,sm8150-smmu-500 120 - qcom,sm8250-smmu-500 121 - const: qcom,adreno-smmu 122 - const: arm,mmu-500 123 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 124 items: 125 - enum: 126 - qcom,msm8996-smmu-v2 127 - qcom,sc7180-smmu-v2 128 - qcom,sdm630-smmu-v2 129 - qcom,sdm670-smmu-v2 130 - qcom,sdm845-smmu-v2 131 - qcom,sm6350-smmu-v2 132 - qcom,sm7150-smmu-v2 133 - const: qcom,adreno-smmu 134 - const: qcom,smmu-v2 135 - description: Qcom Adreno GPUs on Google Cheza platform 136 items: 137 - const: qcom,sdm845-smmu-v2 138 - const: qcom,smmu-v2 139 - description: Marvell SoCs implementing "arm,mmu-500" 140 items: 141 - const: marvell,ap806-smmu-500 142 - const: arm,mmu-500 143 - description: NVIDIA SoCs that require memory controller interaction 144 and may program multiple ARM MMU-500s identically with the memory 145 controller interleaving translations between multiple instances 146 for improved performance. 147 items: 148 - enum: 149 - nvidia,tegra186-smmu 150 - nvidia,tegra194-smmu 151 - nvidia,tegra234-smmu 152 - const: nvidia,smmu-500 153 - items: 154 - const: arm,mmu-500 155 - const: arm,smmu-v2 156 - items: 157 - enum: 158 - arm,mmu-400 159 - arm,mmu-401 160 - const: arm,smmu-v1 161 - enum: 162 - arm,smmu-v1 163 - arm,smmu-v2 164 - arm,mmu-400 165 - arm,mmu-401 166 - arm,mmu-500 167 - cavium,smmu-v2 168 169 reg: 170 minItems: 1 171 maxItems: 2 172 173 '#global-interrupts': 174 description: The number of global interrupts exposed by the device. 175 $ref: /schemas/types.yaml#/definitions/uint32 176 minimum: 0 177 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 178 179 '#iommu-cells': 180 enum: [ 1, 2 ] 181 description: | 182 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 183 value of 1, each IOMMU specifier represents a distinct stream ID emitted 184 by that device into the relevant SMMU. 185 186 SMMUs with stream matching support and complex masters may use a value of 187 2, where the second cell of the IOMMU specifier represents an SMR mask to 188 combine with the ID in the first cell. Care must be taken to ensure the 189 set of matched IDs does not result in conflicts. 190 191 interrupts: 192 minItems: 1 193 maxItems: 388 # 260 plus 128 contexts 194 description: | 195 Interrupt list, with the first #global-interrupts entries corresponding to 196 the global interrupts and any following entries corresponding to context 197 interrupts, specified in order of their indexing by the SMMU. 198 199 For SMMUv2 implementations, there must be exactly one interrupt per 200 context bank. In the case of a single, combined interrupt, it must be 201 listed multiple times. 202 203 dma-coherent: 204 description: | 205 Present if page table walks made by the SMMU are cache coherent with the 206 CPU. 207 208 NOTE: this only applies to the SMMU itself, not masters connected 209 upstream of the SMMU. 210 211 calxeda,smmu-secure-config-access: 212 type: boolean 213 description: 214 Enable proper handling of buggy implementations that always use secure 215 access to SMMU configuration registers. In this case non-secure aliases of 216 secure registers have to be used during SMMU configuration. 217 218 stream-match-mask: 219 $ref: /schemas/types.yaml#/definitions/uint32 220 description: | 221 For SMMUs supporting stream matching and using #iommu-cells = <1>, 222 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 223 be programmed into the SMRn.MASK field of every stream match register 224 used). For cases where it is desirable to ignore some portion of every 225 Stream ID (e.g. for certain MMU-500 configurations given globally unique 226 input IDs). This property is not valid for SMMUs using stream indexing, or 227 using stream matching with #iommu-cells = <2>, and may be ignored if 228 present in such cases. 229 230 clock-names: 231 minItems: 1 232 maxItems: 7 233 234 clocks: 235 minItems: 1 236 maxItems: 7 237 238 power-domains: 239 minItems: 1 240 maxItems: 3 241 242 nvidia,memory-controller: 243 description: | 244 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 245 The memory controller needs to be programmed with a mapping of memory 246 client IDs to ARM SMMU stream IDs. 247 248 If this property is absent, the mapping programmed by early firmware 249 will be used and it is not guaranteed that IOMMU translations will be 250 enabled for any given device. 251 $ref: /schemas/types.yaml#/definitions/phandle 252 253required: 254 - compatible 255 - reg 256 - '#global-interrupts' 257 - '#iommu-cells' 258 - interrupts 259 260additionalProperties: false 261 262allOf: 263 - if: 264 properties: 265 compatible: 266 contains: 267 enum: 268 - nvidia,tegra186-smmu 269 - nvidia,tegra194-smmu 270 - nvidia,tegra234-smmu 271 then: 272 properties: 273 reg: 274 minItems: 1 275 maxItems: 2 276 277 # The reference to the memory controller is required to ensure that the 278 # memory client to stream ID mapping can be done synchronously with the 279 # IOMMU attachment. 280 required: 281 - nvidia,memory-controller 282 else: 283 properties: 284 reg: 285 maxItems: 1 286 287 - if: 288 properties: 289 compatible: 290 contains: 291 enum: 292 - qcom,msm8998-smmu-v2 293 - qcom,sdm630-smmu-v2 294 then: 295 anyOf: 296 - properties: 297 clock-names: 298 items: 299 - const: bus 300 clocks: 301 items: 302 - description: bus clock required for downstream bus access and for 303 the smmu ptw 304 - properties: 305 clock-names: 306 items: 307 - const: iface 308 - const: mem 309 - const: mem_iface 310 clocks: 311 items: 312 - description: interface clock required to access smmu's registers 313 through the TCU's programming interface. 314 - description: bus clock required for memory access 315 - description: bus clock required for GPU memory access 316 - properties: 317 clock-names: 318 items: 319 - const: iface-mm 320 - const: iface-smmu 321 - const: bus-smmu 322 clocks: 323 items: 324 - description: interface clock required to access mnoc's registers 325 through the TCU's programming interface. 326 - description: interface clock required to access smmu's registers 327 through the TCU's programming interface. 328 - description: bus clock required for the smmu ptw 329 330 - if: 331 properties: 332 compatible: 333 contains: 334 enum: 335 - qcom,sm6375-smmu-v2 336 then: 337 anyOf: 338 - properties: 339 clock-names: 340 items: 341 - const: bus 342 clocks: 343 items: 344 - description: bus clock required for downstream bus access and for 345 the smmu ptw 346 - properties: 347 clock-names: 348 items: 349 - const: iface 350 - const: mem 351 - const: mem_iface 352 clocks: 353 items: 354 - description: interface clock required to access smmu's registers 355 through the TCU's programming interface. 356 - description: bus clock required for memory access 357 - description: bus clock required for GPU memory access 358 - properties: 359 clock-names: 360 items: 361 - const: iface-mm 362 - const: iface-smmu 363 - const: bus-mm 364 - const: bus-smmu 365 clocks: 366 items: 367 - description: interface clock required to access mnoc's registers 368 through the TCU's programming interface. 369 - description: interface clock required to access smmu's registers 370 through the TCU's programming interface. 371 - description: bus clock required for downstream bus access 372 - description: bus clock required for the smmu ptw 373 374 - if: 375 properties: 376 compatible: 377 contains: 378 enum: 379 - qcom,msm8996-smmu-v2 380 - qcom,sc7180-smmu-v2 381 - qcom,sdm845-smmu-v2 382 then: 383 properties: 384 clock-names: 385 items: 386 - const: bus 387 - const: iface 388 389 clocks: 390 items: 391 - description: bus clock required for downstream bus access and for 392 the smmu ptw 393 - description: interface clock required to access smmu's registers 394 through the TCU's programming interface. 395 396 - if: 397 properties: 398 compatible: 399 contains: 400 enum: 401 - qcom,qcs8300-smmu-500 402 - qcom,sa8775p-smmu-500 403 - qcom,sc7280-smmu-500 404 - qcom,sc8280xp-smmu-500 405 then: 406 properties: 407 clock-names: 408 items: 409 - const: gcc_gpu_memnoc_gfx_clk 410 - const: gcc_gpu_snoc_dvm_gfx_clk 411 - const: gpu_cc_ahb_clk 412 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 413 - const: gpu_cc_cx_gmu_clk 414 - const: gpu_cc_hub_cx_int_clk 415 - const: gpu_cc_hub_aon_clk 416 417 clocks: 418 items: 419 - description: GPU memnoc_gfx clock 420 - description: GPU snoc_dvm_gfx clock 421 - description: GPU ahb clock 422 - description: GPU hlos1_vote_GPU smmu clock 423 - description: GPU cx_gmu clock 424 - description: GPU hub_cx_int clock 425 - description: GPU hub_aon clock 426 427 - if: 428 properties: 429 compatible: 430 contains: 431 enum: 432 - qcom,sc8180x-smmu-500 433 - qcom,sm6350-smmu-v2 434 - qcom,sm7150-smmu-v2 435 - qcom,sm8150-smmu-500 436 - qcom,sm8250-smmu-500 437 then: 438 properties: 439 clock-names: 440 items: 441 - const: ahb 442 - const: bus 443 - const: iface 444 445 clocks: 446 items: 447 - description: bus clock required for AHB bus access 448 - description: bus clock required for downstream bus access and for 449 the smmu ptw 450 - description: interface clock required to access smmu's registers 451 through the TCU's programming interface. 452 453 - if: 454 properties: 455 compatible: 456 items: 457 - enum: 458 - qcom,sm8350-smmu-500 459 - const: qcom,adreno-smmu 460 - const: qcom,smmu-500 461 - const: arm,mmu-500 462 then: 463 properties: 464 clock-names: 465 items: 466 - const: bus 467 - const: iface 468 - const: ahb 469 - const: hlos1_vote_gpu_smmu 470 - const: cx_gmu 471 - const: hub_cx_int 472 - const: hub_aon 473 clocks: 474 minItems: 7 475 maxItems: 7 476 477 - if: 478 properties: 479 compatible: 480 items: 481 - enum: 482 - qcom,qcm2290-smmu-500 483 - qcom,qcs615-smmu-500 484 - qcom,sm6115-smmu-500 485 - qcom,sm6125-smmu-500 486 - const: qcom,adreno-smmu 487 - const: qcom,smmu-500 488 - const: arm,mmu-500 489 then: 490 properties: 491 clock-names: 492 items: 493 - const: mem 494 - const: hlos 495 - const: iface 496 497 clocks: 498 items: 499 - description: GPU memory bus clock 500 - description: Voter clock required for HLOS SMMU access 501 - description: Interface clock required for register access 502 503 - if: 504 properties: 505 compatible: 506 items: 507 - const: qcom,sm8450-smmu-500 508 - const: qcom,adreno-smmu 509 - const: qcom,smmu-500 510 - const: arm,mmu-500 511 512 then: 513 properties: 514 clock-names: 515 items: 516 - const: gmu 517 - const: hub 518 - const: hlos 519 - const: bus 520 - const: iface 521 - const: ahb 522 523 clocks: 524 items: 525 - description: GMU clock 526 - description: GPU HUB clock 527 - description: HLOS vote clock 528 - description: GPU memory bus clock 529 - description: GPU SNoC bus clock 530 - description: GPU AHB clock 531 532 - if: 533 properties: 534 compatible: 535 items: 536 - enum: 537 - qcom,sar2130p-smmu-500 538 - qcom,sm8550-smmu-500 539 - qcom,sm8650-smmu-500 540 - qcom,x1e80100-smmu-500 541 - const: qcom,adreno-smmu 542 - const: qcom,smmu-500 543 - const: arm,mmu-500 544 then: 545 properties: 546 clock-names: 547 items: 548 - const: hlos 549 - const: bus 550 - const: iface 551 - const: ahb 552 553 clocks: 554 items: 555 - description: HLOS vote clock 556 - description: GPU memory bus clock 557 - description: GPU SNoC bus clock 558 - description: GPU AHB clock 559 560 - if: 561 properties: 562 compatible: 563 items: 564 - const: qcom,sm8750-smmu-500 565 - const: qcom,adreno-smmu 566 - const: qcom,smmu-500 567 - const: arm,mmu-500 568 then: 569 properties: 570 clock-names: 571 items: 572 - const: hlos 573 clocks: 574 items: 575 - description: HLOS vote clock 576 577 # Disallow clocks for all other platforms with specific compatibles 578 - if: 579 properties: 580 compatible: 581 contains: 582 enum: 583 - cavium,smmu-v2 584 - marvell,ap806-smmu-500 585 - nvidia,smmu-500 586 - qcom,qdu1000-smmu-500 587 - qcom,sa8255p-smmu-500 588 - qcom,sc7180-smmu-500 589 - qcom,sdm670-smmu-500 590 - qcom,sdm845-smmu-500 591 - qcom,sdx55-smmu-500 592 - qcom,sdx65-smmu-500 593 - qcom,sm6350-smmu-500 594 - qcom,sm6375-smmu-500 595 then: 596 properties: 597 clock-names: false 598 clocks: false 599 600 - if: 601 properties: 602 compatible: 603 contains: 604 const: qcom,sm6375-smmu-500 605 then: 606 properties: 607 power-domains: 608 items: 609 - description: SNoC MMU TBU RT GDSC 610 - description: SNoC MMU TBU NRT GDSC 611 - description: SNoC TURING MMU TBU0 GDSC 612 613 required: 614 - power-domains 615 else: 616 properties: 617 power-domains: 618 maxItems: 1 619 620examples: 621 - |+ 622 /* SMMU with stream matching or stream indexing */ 623 smmu1: iommu@ba5e0000 { 624 compatible = "arm,smmu-v1"; 625 reg = <0xba5e0000 0x10000>; 626 #global-interrupts = <2>; 627 interrupts = <0 32 4>, 628 <0 33 4>, 629 <0 34 4>, /* This is the first context interrupt */ 630 <0 35 4>, 631 <0 36 4>, 632 <0 37 4>; 633 #iommu-cells = <1>; 634 }; 635 636 /* device with two stream IDs, 0 and 7 */ 637 master1 { 638 iommus = <&smmu1 0>, 639 <&smmu1 7>; 640 }; 641 642 643 /* SMMU with stream matching */ 644 smmu2: iommu@ba5f0000 { 645 compatible = "arm,smmu-v1"; 646 reg = <0xba5f0000 0x10000>; 647 #global-interrupts = <2>; 648 interrupts = <0 38 4>, 649 <0 39 4>, 650 <0 40 4>, /* This is the first context interrupt */ 651 <0 41 4>, 652 <0 42 4>, 653 <0 43 4>; 654 #iommu-cells = <2>; 655 }; 656 657 /* device with stream IDs 0 and 7 */ 658 master2 { 659 iommus = <&smmu2 0 0>, 660 <&smmu2 7 0>; 661 }; 662 663 /* device with stream IDs 1, 17, 33 and 49 */ 664 master3 { 665 iommus = <&smmu2 1 0x30>; 666 }; 667 668 669 /* ARM MMU-500 with 10-bit stream ID input configuration */ 670 smmu3: iommu@ba600000 { 671 compatible = "arm,mmu-500", "arm,smmu-v2"; 672 reg = <0xba600000 0x10000>; 673 #global-interrupts = <2>; 674 interrupts = <0 44 4>, 675 <0 45 4>, 676 <0 46 4>, /* This is the first context interrupt */ 677 <0 47 4>, 678 <0 48 4>, 679 <0 49 4>; 680 #iommu-cells = <1>; 681 /* always ignore appended 5-bit TBU number */ 682 stream-match-mask = <0x7c00>; 683 }; 684 685 bus { 686 /* bus whose child devices emit one unique 10-bit stream 687 ID each, but may master through multiple SMMU TBUs */ 688 iommu-map = <0 &smmu3 0 0x400>; 689 690 691 }; 692 693 - |+ 694 /* Qcom's arm,smmu-v2 implementation */ 695 #include <dt-bindings/interrupt-controller/arm-gic.h> 696 #include <dt-bindings/interrupt-controller/irq.h> 697 smmu4: iommu@d00000 { 698 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 699 reg = <0xd00000 0x10000>; 700 701 #global-interrupts = <1>; 702 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 705 #iommu-cells = <1>; 706 power-domains = <&mmcc 0>; 707 708 clocks = <&mmcc 123>, 709 <&mmcc 124>; 710 clock-names = "bus", "iface"; 711 }; 712