1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Texas Instruments K3 Interrupt Router 8 9maintainers: 10 - Lokesh Vutla <lokeshvutla@ti.com> 11 12allOf: 13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 14 15description: | 16 The Interrupt Router (INTR) module provides a mechanism to mux M 17 interrupt inputs to N interrupt outputs, where all M inputs are selectable 18 to be driven per N output. 19 20 Interrupt Router 21 +----------------------+ 22 | Inputs Outputs | 23 +-------+ | +------+ +-----+ | 24 | GPIO |----------->| | irq0 | | 0 | | Host IRQ 25 +-------+ | +------+ +-----+ | controller 26 | . . | +-------+ 27 +-------+ | . . |----->| IRQ | 28 | INTA |----------->| . . | +-------+ 29 +-------+ | . +-----+ | 30 | +------+ | N | | 31 | | irqM | +-----+ | 32 | +------+ | 33 | | 34 +----------------------+ 35 36 There is one register per output (MUXCNTL_N) that controls the selection. 37 Configuration of these MUXCNTL_N registers is done by a system controller 38 (like the Device Memory and Security Controller on K3 AM654 SoC). System 39 controller will keep track of the used and unused registers within the Router. 40 Driver should request the system controller to get the range of GIC IRQs 41 assigned to the requesting hosts. It is the drivers responsibility to keep 42 track of Host IRQs. 43 44 Communication between the host processor running an OS and the system 45 controller happens through a protocol called TI System Control Interface 46 (TISCI protocol). 47 48properties: 49 compatible: 50 const: ti,sci-intr 51 52 ti,intr-trigger-type: 53 $ref: /schemas/types.yaml#/definitions/uint32 54 enum: [1, 4] 55 description: | 56 Should be one of the following. 57 1 = If intr supports edge triggered interrupts. 58 4 = If intr supports level triggered interrupts. 59 60 reg: 61 maxItems: 1 62 63 interrupt-controller: true 64 65 '#interrupt-cells': 66 enum: [1, 2] 67 description: | 68 Number of cells in interrupt specifier. Depends on ti,intr-trigger-type: 69 - If ti,intr-trigger-type is present: must be 1 70 The 1st cell should contain interrupt router input hw number. 71 - If ti,intr-trigger-type is absent: must be 2 72 The 1st cell should contain interrupt router input hw number. 73 The 2nd cell should contain interrupt trigger type (preserved by router). 74 75 ti,interrupt-ranges: 76 $ref: /schemas/types.yaml#/definitions/uint32-matrix 77 description: | 78 Interrupt ranges that converts the INTR output hw irq numbers 79 to parents's input interrupt numbers. 80 items: 81 items: 82 - description: | 83 "output_irq" specifies the base for intr output irq 84 - description: | 85 "parent's input irq" specifies the base for parent irq 86 - description: | 87 "limit" specifies the limit for translation 88 89if: 90 required: 91 - ti,intr-trigger-type 92then: 93 properties: 94 '#interrupt-cells': 95 const: 1 96 description: Interrupt ID only. Interrupt type is specified globally 97else: 98 properties: 99 '#interrupt-cells': 100 const: 2 101 description: Interrupt ID and corresponding interrupt type 102 103required: 104 - compatible 105 - interrupt-controller 106 - '#interrupt-cells' 107 - ti,sci 108 - ti,sci-dev-id 109 - ti,interrupt-ranges 110 111unevaluatedProperties: false 112 113examples: 114 - | 115 main_gpio_intr: interrupt-controller0 { 116 compatible = "ti,sci-intr"; 117 ti,intr-trigger-type = <1>; 118 interrupt-controller; 119 interrupt-parent = <&gic500>; 120 #interrupt-cells = <1>; 121 ti,sci = <&dmsc>; 122 ti,sci-dev-id = <131>; 123 ti,interrupt-ranges = <0 360 32>; 124 }; 125 126 - | 127 interrupt-controller { 128 compatible = "ti,sci-intr"; 129 interrupt-controller; 130 interrupt-parent = <&gic500>; 131 #interrupt-cells = <2>; 132 ti,sci = <&dmsc>; 133 ti,sci-dev-id = <131>; 134 ti,interrupt-ranges = <0 360 32>; 135 }; 136