1*591b00ccSRaphael Gallais-Pou# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*591b00ccSRaphael Gallais-Pou%YAML 1.2 3*591b00ccSRaphael Gallais-Pou--- 4*591b00ccSRaphael Gallais-Pou$id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml# 5*591b00ccSRaphael Gallais-Pou$schema: http://devicetree.org/meta-schemas/core.yaml# 6*591b00ccSRaphael Gallais-Pou 7*591b00ccSRaphael Gallais-Poutitle: STMicroelectronics STi System Configuration Controlled IRQs 8*591b00ccSRaphael Gallais-Pou 9*591b00ccSRaphael Gallais-Poumaintainers: 10*591b00ccSRaphael Gallais-Pou - Patrice Chotard <patrice.chotard@foss.st.com> 11*591b00ccSRaphael Gallais-Pou 12*591b00ccSRaphael Gallais-Poudescription: 13*591b00ccSRaphael Gallais-Pou On STi based systems; External, CTI (Core Sight), PMU (Performance 14*591b00ccSRaphael Gallais-Pou Management), and PL310 L2 Cache IRQs are controlled using System 15*591b00ccSRaphael Gallais-Pou Configuration registers. This device is used to unmask them prior to use. 16*591b00ccSRaphael Gallais-Pou 17*591b00ccSRaphael Gallais-Pouproperties: 18*591b00ccSRaphael Gallais-Pou compatible: 19*591b00ccSRaphael Gallais-Pou const: st,stih407-irq-syscfg 20*591b00ccSRaphael Gallais-Pou 21*591b00ccSRaphael Gallais-Pou st,syscfg: 22*591b00ccSRaphael Gallais-Pou description: Phandle to Cortex-A9 IRQ system config registers 23*591b00ccSRaphael Gallais-Pou $ref: /schemas/types.yaml#/definitions/phandle 24*591b00ccSRaphael Gallais-Pou 25*591b00ccSRaphael Gallais-Pou st,irq-device: 26*591b00ccSRaphael Gallais-Pou description: Array of IRQs to enable. 27*591b00ccSRaphael Gallais-Pou $ref: /schemas/types.yaml#/definitions/uint32-array 28*591b00ccSRaphael Gallais-Pou items: 29*591b00ccSRaphael Gallais-Pou - description: Enable the IRQ of the channel one. 30*591b00ccSRaphael Gallais-Pou - description: Enable the IRQ of the channel two. 31*591b00ccSRaphael Gallais-Pou 32*591b00ccSRaphael Gallais-Pou st,fiq-device: 33*591b00ccSRaphael Gallais-Pou description: Array of FIQs to enable. 34*591b00ccSRaphael Gallais-Pou $ref: /schemas/types.yaml#/definitions/uint32-array 35*591b00ccSRaphael Gallais-Pou items: 36*591b00ccSRaphael Gallais-Pou - description: Enable the IRQ of the channel one. 37*591b00ccSRaphael Gallais-Pou - description: Enable the IRQ of the channel two. 38*591b00ccSRaphael Gallais-Pou 39*591b00ccSRaphael Gallais-Pou st,invert-ext: 40*591b00ccSRaphael Gallais-Pou description: External IRQs can be inverted at will. This property inverts 41*591b00ccSRaphael Gallais-Pou these three IRQs using bitwise logic, each one being encoded respectively 42*591b00ccSRaphael Gallais-Pou on the first, second and fourth bit. 43*591b00ccSRaphael Gallais-Pou $ref: /schemas/types.yaml#/definitions/uint32 44*591b00ccSRaphael Gallais-Pou enum: [ 1, 2, 3, 4, 5, 6 ] 45*591b00ccSRaphael Gallais-Pou 46*591b00ccSRaphael Gallais-Pourequired: 47*591b00ccSRaphael Gallais-Pou - compatible 48*591b00ccSRaphael Gallais-Pou - st,syscfg 49*591b00ccSRaphael Gallais-Pou - st,irq-device 50*591b00ccSRaphael Gallais-Pou - st,fiq-device 51*591b00ccSRaphael Gallais-Pou 52*591b00ccSRaphael Gallais-PouadditionalProperties: false 53*591b00ccSRaphael Gallais-Pou 54*591b00ccSRaphael Gallais-Pouexamples: 55*591b00ccSRaphael Gallais-Pou - | 56*591b00ccSRaphael Gallais-Pou #include <dt-bindings/interrupt-controller/irq-st.h> 57*591b00ccSRaphael Gallais-Pou irq-syscfg { 58*591b00ccSRaphael Gallais-Pou compatible = "st,stih407-irq-syscfg"; 59*591b00ccSRaphael Gallais-Pou st,syscfg = <&syscfg_cpu>; 60*591b00ccSRaphael Gallais-Pou st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 61*591b00ccSRaphael Gallais-Pou <ST_IRQ_SYSCFG_PMU_1>; 62*591b00ccSRaphael Gallais-Pou st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 63*591b00ccSRaphael Gallais-Pou <ST_IRQ_SYSCFG_DISABLED>; 64*591b00ccSRaphael Gallais-Pou }; 65*591b00ccSRaphael Gallais-Pou... 66