1*eb3fcf00SRob Herring* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) 2*eb3fcf00SRob Herring 3*eb3fcf00SRob HerringProperties: 4*eb3fcf00SRob Herring 5*eb3fcf00SRob Herring- compatible: "snps,archs-intc" 6*eb3fcf00SRob Herring- interrupt-controller: This is an interrupt controller. 7*eb3fcf00SRob Herring- #interrupt-cells: Must be <1>. 8*eb3fcf00SRob Herring 9*eb3fcf00SRob Herring Single Cell "interrupts" property of a device specifies the IRQ number 10*eb3fcf00SRob Herring between 16 to 256 11*eb3fcf00SRob Herring 12*eb3fcf00SRob Herring intc accessed via the special ARC AUX register interface, hence "reg" property 13*eb3fcf00SRob Herring is not specified. 14*eb3fcf00SRob Herring 15*eb3fcf00SRob HerringExample: 16*eb3fcf00SRob Herring 17*eb3fcf00SRob Herring intc: interrupt-controller { 18*eb3fcf00SRob Herring compatible = "snps,archs-intc"; 19*eb3fcf00SRob Herring interrupt-controller; 20*eb3fcf00SRob Herring #interrupt-cells = <1>; 21*eb3fcf00SRob Herring interrupts = <16 17 18 19 20 21 22 23 24 25>; 22*eb3fcf00SRob Herring }; 23