1eb3fcf00SRob Herring* ARC-HS Interrupt Distribution Unit 2eb3fcf00SRob Herring 301449985SMischa Jonker This optional 2nd level interrupt controller can be used in SMP configurations 401449985SMischa Jonker for dynamic IRQ routing, load balancing of common/external IRQs towards core 501449985SMischa Jonker intc. 6eb3fcf00SRob Herring 7eb3fcf00SRob HerringProperties: 8eb3fcf00SRob Herring 9eb3fcf00SRob Herring- compatible: "snps,archs-idu-intc" 10eb3fcf00SRob Herring- interrupt-controller: This is an interrupt controller. 11*d85f6b93SMischa Jonker- #interrupt-cells: Must be <1> or <2>. 12eb3fcf00SRob Herring 13*d85f6b93SMischa Jonker Value of the first cell specifies the "common" IRQ from peripheral to IDU. 14*d85f6b93SMischa Jonker Number N of the particular interrupt line of IDU corresponds to the line N+24 15*d85f6b93SMischa Jonker of the core interrupt controller. 16*d85f6b93SMischa Jonker 17*d85f6b93SMischa Jonker The (optional) second cell specifies any of the following flags: 18*d85f6b93SMischa Jonker - bits[3:0] trigger type and level flags 19*d85f6b93SMischa Jonker 1 = low-to-high edge triggered 20*d85f6b93SMischa Jonker 2 = NOT SUPPORTED (high-to-low edge triggered) 21*d85f6b93SMischa Jonker 4 = active high level-sensitive <<< DEFAULT 22*d85f6b93SMischa Jonker 8 = NOT SUPPORTED (active low level-sensitive) 23*d85f6b93SMischa Jonker When no second cell is specified, the interrupt is assumed to be level 24*d85f6b93SMischa Jonker sensitive. 2592fdb527SYuriy Kolerov 2601449985SMischa Jonker The interrupt controller is accessed via the special ARC AUX register 2701449985SMischa Jonker interface, hence "reg" property is not specified. 28eb3fcf00SRob Herring 29eb3fcf00SRob HerringExample: 30eb3fcf00SRob Herring core_intc: core-interrupt-controller { 31eb3fcf00SRob Herring compatible = "snps,archs-intc"; 32eb3fcf00SRob Herring interrupt-controller; 33eb3fcf00SRob Herring #interrupt-cells = <1>; 34eb3fcf00SRob Herring }; 35eb3fcf00SRob Herring 36eb3fcf00SRob Herring idu_intc: idu-interrupt-controller { 37eb3fcf00SRob Herring compatible = "snps,archs-idu-intc"; 38eb3fcf00SRob Herring interrupt-controller; 39eb3fcf00SRob Herring interrupt-parent = <&core_intc>; 40ec69b269SYuriy Kolerov #interrupt-cells = <1>; 41eb3fcf00SRob Herring }; 42eb3fcf00SRob Herring 43eb3fcf00SRob Herring some_device: serial@c0fc1000 { 44eb3fcf00SRob Herring interrupt-parent = <&idu_intc>; 45ec69b269SYuriy Kolerov interrupts = <0>; /* upstream idu IRQ #24 */ 46eb3fcf00SRob Herring }; 47