xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - andestech,qilai-plic
57              - renesas,r9a07g043-plic
58          - const: andestech,nceplic100
59      - items:
60          - enum:
61              - canaan,k210-plic
62              - sifive,fu540-c000-plic
63              - spacemit,k1-plic
64              - starfive,jh7100-plic
65              - starfive,jh7110-plic
66          - const: sifive,plic-1.0.0
67      - items:
68          - enum:
69              - allwinner,sun20i-d1-plic
70              - sophgo,cv1800b-plic
71              - sophgo,cv1812h-plic
72              - sophgo,sg2002-plic
73              - sophgo,sg2042-plic
74              - sophgo,sg2044-plic
75              - thead,th1520-plic
76          - const: thead,c900-plic
77      - items:
78          - const: sifive,plic-1.0.0
79          - const: riscv,plic0
80        deprecated: true
81        description: For the QEMU virt machine only
82
83  reg:
84    maxItems: 1
85
86  '#address-cells':
87    const: 0
88
89  '#interrupt-cells': true
90
91  interrupt-controller: true
92
93  interrupts-extended:
94    minItems: 1
95    maxItems: 15872
96    description:
97      Specifies which contexts are connected to the PLIC, with "-1" specifying
98      that a context is not present. Each node pointed to should be a
99      riscv,cpu-intc node, which has a riscv node as parent.
100
101  riscv,ndev:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      Specifies how many external interrupts are supported by this controller.
105
106  clocks: true
107
108  power-domains: true
109
110  resets: true
111
112required:
113  - compatible
114  - '#address-cells'
115  - '#interrupt-cells'
116  - interrupt-controller
117  - reg
118  - interrupts-extended
119  - riscv,ndev
120
121allOf:
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - andestech,nceplic100
128              - thead,c900-plic
129
130    then:
131      properties:
132        '#interrupt-cells':
133          const: 2
134
135    else:
136      properties:
137        '#interrupt-cells':
138          const: 1
139
140  - if:
141      properties:
142        compatible:
143          contains:
144            const: renesas,r9a07g043-plic
145
146    then:
147      properties:
148        clocks:
149          maxItems: 1
150
151        power-domains:
152          maxItems: 1
153
154        resets:
155          maxItems: 1
156
157      required:
158        - clocks
159        - power-domains
160        - resets
161
162additionalProperties: false
163
164examples:
165  - |
166    plic: interrupt-controller@c000000 {
167      #address-cells = <0>;
168      #interrupt-cells = <1>;
169      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
170      interrupt-controller;
171      interrupts-extended = <&cpu0_intc 11>,
172                            <&cpu1_intc 11>, <&cpu1_intc 9>,
173                            <&cpu2_intc 11>, <&cpu2_intc 9>,
174                            <&cpu3_intc 11>, <&cpu3_intc 9>,
175                            <&cpu4_intc 11>, <&cpu4_intc 9>;
176      reg = <0xc000000 0x4000000>;
177      riscv,ndev = <10>;
178    };
179