xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision 7f81907b7e3f93dfed2e903af52659baa4944341) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - renesas,r9a07g043-plic
57          - const: andestech,nceplic100
58      - items:
59          - enum:
60              - canaan,k210-plic
61              - sifive,fu540-c000-plic
62              - spacemit,k1-plic
63              - starfive,jh7100-plic
64              - starfive,jh7110-plic
65          - const: sifive,plic-1.0.0
66      - items:
67          - enum:
68              - allwinner,sun20i-d1-plic
69              - sophgo,cv1800b-plic
70              - sophgo,cv1812h-plic
71              - sophgo,sg2002-plic
72              - sophgo,sg2042-plic
73              - sophgo,sg2044-plic
74              - thead,th1520-plic
75          - const: thead,c900-plic
76      - items:
77          - const: sifive,plic-1.0.0
78          - const: riscv,plic0
79        deprecated: true
80        description: For the QEMU virt machine only
81
82  reg:
83    maxItems: 1
84
85  '#address-cells':
86    const: 0
87
88  '#interrupt-cells': true
89
90  interrupt-controller: true
91
92  interrupts-extended:
93    minItems: 1
94    maxItems: 15872
95    description:
96      Specifies which contexts are connected to the PLIC, with "-1" specifying
97      that a context is not present. Each node pointed to should be a
98      riscv,cpu-intc node, which has a riscv node as parent.
99
100  riscv,ndev:
101    $ref: /schemas/types.yaml#/definitions/uint32
102    description:
103      Specifies how many external interrupts are supported by this controller.
104
105  clocks: true
106
107  power-domains: true
108
109  resets: true
110
111required:
112  - compatible
113  - '#address-cells'
114  - '#interrupt-cells'
115  - interrupt-controller
116  - reg
117  - interrupts-extended
118  - riscv,ndev
119
120allOf:
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - andestech,nceplic100
127              - thead,c900-plic
128
129    then:
130      properties:
131        '#interrupt-cells':
132          const: 2
133
134    else:
135      properties:
136        '#interrupt-cells':
137          const: 1
138
139  - if:
140      properties:
141        compatible:
142          contains:
143            const: renesas,r9a07g043-plic
144
145    then:
146      properties:
147        clocks:
148          maxItems: 1
149
150        power-domains:
151          maxItems: 1
152
153        resets:
154          maxItems: 1
155
156      required:
157        - clocks
158        - power-domains
159        - resets
160
161additionalProperties: false
162
163examples:
164  - |
165    plic: interrupt-controller@c000000 {
166      #address-cells = <0>;
167      #interrupt-cells = <1>;
168      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
169      interrupt-controller;
170      interrupts-extended = <&cpu0_intc 11>,
171                            <&cpu1_intc 11>, <&cpu1_intc 9>,
172                            <&cpu2_intc 11>, <&cpu2_intc 9>,
173                            <&cpu3_intc 11>, <&cpu3_intc 9>,
174                            <&cpu4_intc 11>, <&cpu4_intc 9>;
175      reg = <0xc000000 0x4000000>;
176      riscv,ndev = <10>;
177    };
178