xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision 55a42f78ffd386e01a5404419f8c5ded7db70a21) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - andestech,qilai-plic
57              - renesas,r9a07g043-plic
58          - const: andestech,nceplic100
59      - items:
60          - enum:
61              - canaan,k210-plic
62              - eswin,eic7700-plic
63              - sifive,fu540-c000-plic
64              - spacemit,k1-plic
65              - starfive,jh7100-plic
66              - starfive,jh7110-plic
67          - const: sifive,plic-1.0.0
68      - items:
69          - enum:
70              - allwinner,sun20i-d1-plic
71              - sophgo,cv1800b-plic
72              - sophgo,cv1812h-plic
73              - sophgo,sg2002-plic
74              - sophgo,sg2042-plic
75              - sophgo,sg2044-plic
76              - thead,th1520-plic
77          - const: thead,c900-plic
78      - items:
79          - const: sifive,plic-1.0.0
80          - const: riscv,plic0
81        deprecated: true
82        description: For the QEMU virt machine only
83
84  reg:
85    maxItems: 1
86
87  '#address-cells':
88    const: 0
89
90  '#interrupt-cells': true
91
92  interrupt-controller: true
93
94  interrupts-extended:
95    minItems: 1
96    maxItems: 15872
97    description:
98      Specifies which contexts are connected to the PLIC, with "-1" specifying
99      that a context is not present. Each node pointed to should be a
100      riscv,cpu-intc node, which has a riscv node as parent.
101
102  riscv,ndev:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    description:
105      Specifies how many external interrupts are supported by this controller.
106
107  clocks: true
108
109  power-domains: true
110
111  resets: true
112
113required:
114  - compatible
115  - '#address-cells'
116  - '#interrupt-cells'
117  - interrupt-controller
118  - reg
119  - interrupts-extended
120  - riscv,ndev
121
122allOf:
123  - if:
124      properties:
125        compatible:
126          contains:
127            enum:
128              - andestech,nceplic100
129              - thead,c900-plic
130
131    then:
132      properties:
133        '#interrupt-cells':
134          const: 2
135
136    else:
137      properties:
138        '#interrupt-cells':
139          const: 1
140
141  - if:
142      properties:
143        compatible:
144          contains:
145            const: renesas,r9a07g043-plic
146
147    then:
148      properties:
149        clocks:
150          maxItems: 1
151
152        power-domains:
153          maxItems: 1
154
155        resets:
156          maxItems: 1
157
158      required:
159        - clocks
160        - power-domains
161        - resets
162
163additionalProperties: false
164
165examples:
166  - |
167    plic: interrupt-controller@c000000 {
168      #address-cells = <0>;
169      #interrupt-cells = <1>;
170      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171      interrupt-controller;
172      interrupts-extended = <&cpu0_intc 11>,
173                            <&cpu1_intc 11>, <&cpu1_intc 9>,
174                            <&cpu2_intc 11>, <&cpu2_intc 9>,
175                            <&cpu3_intc 11>, <&cpu3_intc 9>,
176                            <&cpu4_intc 11>, <&cpu4_intc 9>;
177      reg = <0xc000000 0x4000000>;
178      riscv,ndev = <10>;
179    };
180