xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - renesas,r9a07g043-plic
57          - const: andestech,nceplic100
58      - items:
59          - enum:
60              - canaan,k210-plic
61              - sifive,fu540-c000-plic
62              - starfive,jh7100-plic
63              - starfive,jh7110-plic
64          - const: sifive,plic-1.0.0
65      - items:
66          - enum:
67              - allwinner,sun20i-d1-plic
68              - thead,th1520-plic
69          - const: thead,c900-plic
70      - items:
71          - const: sifive,plic-1.0.0
72          - const: riscv,plic0
73        deprecated: true
74        description: For the QEMU virt machine only
75
76  reg:
77    maxItems: 1
78
79  '#address-cells':
80    const: 0
81
82  '#interrupt-cells': true
83
84  interrupt-controller: true
85
86  interrupts-extended:
87    minItems: 1
88    maxItems: 15872
89    description:
90      Specifies which contexts are connected to the PLIC, with "-1" specifying
91      that a context is not present. Each node pointed to should be a
92      riscv,cpu-intc node, which has a riscv node as parent.
93
94  riscv,ndev:
95    $ref: /schemas/types.yaml#/definitions/uint32
96    description:
97      Specifies how many external interrupts are supported by this controller.
98
99  clocks: true
100
101  power-domains: true
102
103  resets: true
104
105required:
106  - compatible
107  - '#address-cells'
108  - '#interrupt-cells'
109  - interrupt-controller
110  - reg
111  - interrupts-extended
112  - riscv,ndev
113
114allOf:
115  - if:
116      properties:
117        compatible:
118          contains:
119            enum:
120              - andestech,nceplic100
121              - thead,c900-plic
122
123    then:
124      properties:
125        '#interrupt-cells':
126          const: 2
127
128    else:
129      properties:
130        '#interrupt-cells':
131          const: 1
132
133  - if:
134      properties:
135        compatible:
136          contains:
137            const: renesas,r9a07g043-plic
138
139    then:
140      properties:
141        clocks:
142          maxItems: 1
143
144        power-domains:
145          maxItems: 1
146
147        resets:
148          maxItems: 1
149
150      required:
151        - clocks
152        - power-domains
153        - resets
154
155additionalProperties: false
156
157examples:
158  - |
159    plic: interrupt-controller@c000000 {
160      #address-cells = <0>;
161      #interrupt-cells = <1>;
162      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
163      interrupt-controller;
164      interrupts-extended = <&cpu0_intc 11>,
165                            <&cpu1_intc 11>, <&cpu1_intc 9>,
166                            <&cpu2_intc 11>, <&cpu2_intc 9>,
167                            <&cpu3_intc 11>, <&cpu3_intc 9>,
168                            <&cpu4_intc 11>, <&cpu4_intc 9>;
169      reg = <0xc000000 0x4000000>;
170      riscv,ndev = <10>;
171    };
172