xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision 011f129fee4bd064a3db30ca1a0139548a619482) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - renesas,r9a07g043-plic
57          - const: andestech,nceplic100
58      - items:
59          - enum:
60              - canaan,k210-plic
61              - sifive,fu540-c000-plic
62              - starfive,jh7100-plic
63              - starfive,jh7110-plic
64          - const: sifive,plic-1.0.0
65      - items:
66          - enum:
67              - allwinner,sun20i-d1-plic
68              - sophgo,cv1800b-plic
69              - sophgo,sg2042-plic
70              - thead,th1520-plic
71          - const: thead,c900-plic
72      - items:
73          - const: sifive,plic-1.0.0
74          - const: riscv,plic0
75        deprecated: true
76        description: For the QEMU virt machine only
77
78  reg:
79    maxItems: 1
80
81  '#address-cells':
82    const: 0
83
84  '#interrupt-cells': true
85
86  interrupt-controller: true
87
88  interrupts-extended:
89    minItems: 1
90    maxItems: 15872
91    description:
92      Specifies which contexts are connected to the PLIC, with "-1" specifying
93      that a context is not present. Each node pointed to should be a
94      riscv,cpu-intc node, which has a riscv node as parent.
95
96  riscv,ndev:
97    $ref: /schemas/types.yaml#/definitions/uint32
98    description:
99      Specifies how many external interrupts are supported by this controller.
100
101  clocks: true
102
103  power-domains: true
104
105  resets: true
106
107required:
108  - compatible
109  - '#address-cells'
110  - '#interrupt-cells'
111  - interrupt-controller
112  - reg
113  - interrupts-extended
114  - riscv,ndev
115
116allOf:
117  - if:
118      properties:
119        compatible:
120          contains:
121            enum:
122              - andestech,nceplic100
123              - thead,c900-plic
124
125    then:
126      properties:
127        '#interrupt-cells':
128          const: 2
129
130    else:
131      properties:
132        '#interrupt-cells':
133          const: 1
134
135  - if:
136      properties:
137        compatible:
138          contains:
139            const: renesas,r9a07g043-plic
140
141    then:
142      properties:
143        clocks:
144          maxItems: 1
145
146        power-domains:
147          maxItems: 1
148
149        resets:
150          maxItems: 1
151
152      required:
153        - clocks
154        - power-domains
155        - resets
156
157additionalProperties: false
158
159examples:
160  - |
161    plic: interrupt-controller@c000000 {
162      #address-cells = <0>;
163      #interrupt-cells = <1>;
164      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
165      interrupt-controller;
166      interrupts-extended = <&cpu0_intc 11>,
167                            <&cpu1_intc 11>, <&cpu1_intc 9>,
168                            <&cpu2_intc 11>, <&cpu2_intc 9>,
169                            <&cpu3_intc 11>, <&cpu3_intc 9>,
170                            <&cpu4_intc 11>, <&cpu4_intc 9>;
171      reg = <0xc000000 0x4000000>;
172      riscv,ndev = <10>;
173    };
174