1*a72ab251SAnup Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a72ab251SAnup Patel%YAML 1.2 3*a72ab251SAnup Patel--- 4*a72ab251SAnup Patel$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml# 5*a72ab251SAnup Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a72ab251SAnup Patel 7*a72ab251SAnup Pateltitle: RISC-V RPMI system MSI service group based message proxy 8*a72ab251SAnup Patel 9*a72ab251SAnup Patelmaintainers: 10*a72ab251SAnup Patel - Anup Patel <anup@brainfault.org> 11*a72ab251SAnup Patel 12*a72ab251SAnup Pateldescription: | 13*a72ab251SAnup Patel The RISC-V Platform Management Interface (RPMI) [1] defines a 14*a72ab251SAnup Patel messaging protocol which is modular and extensible. The supervisor 15*a72ab251SAnup Patel software can send/receive RPMI messages via SBI MPXY extension [2] 16*a72ab251SAnup Patel or some dedicated supervisor-mode RPMI transport. 17*a72ab251SAnup Patel 18*a72ab251SAnup Patel The RPMI specification [1] defines system MSI service group which 19*a72ab251SAnup Patel allow application processors to receive MSIs upon system events 20*a72ab251SAnup Patel such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug 21*a72ab251SAnup Patel event, memory hotplug event, etc from the platform microcontroller. 22*a72ab251SAnup Patel The SBI implementation (machine mode firmware or hypervisor) can 23*a72ab251SAnup Patel implement an SBI MPXY channel to allow RPMI system MSI service 24*a72ab251SAnup Patel group access to the supervisor software. 25*a72ab251SAnup Patel 26*a72ab251SAnup Patel =========================================== 27*a72ab251SAnup Patel References 28*a72ab251SAnup Patel =========================================== 29*a72ab251SAnup Patel 30*a72ab251SAnup Patel [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) 31*a72ab251SAnup Patel https://github.com/riscv-non-isa/riscv-rpmi/releases 32*a72ab251SAnup Patel 33*a72ab251SAnup Patel [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) 34*a72ab251SAnup Patel https://github.com/riscv-non-isa/riscv-sbi-doc/releases 35*a72ab251SAnup Patel 36*a72ab251SAnup Patelproperties: 37*a72ab251SAnup Patel compatible: 38*a72ab251SAnup Patel description: 39*a72ab251SAnup Patel Intended for use by the SBI implementation. 40*a72ab251SAnup Patel const: riscv,rpmi-mpxy-system-msi 41*a72ab251SAnup Patel 42*a72ab251SAnup Patel mboxes: 43*a72ab251SAnup Patel maxItems: 1 44*a72ab251SAnup Patel description: 45*a72ab251SAnup Patel Mailbox channel of the underlying RPMI transport. 46*a72ab251SAnup Patel 47*a72ab251SAnup Patel riscv,sbi-mpxy-channel-id: 48*a72ab251SAnup Patel $ref: /schemas/types.yaml#/definitions/uint32 49*a72ab251SAnup Patel description: 50*a72ab251SAnup Patel The SBI MPXY channel id to be used for providing RPMI access to 51*a72ab251SAnup Patel the supervisor software. 52*a72ab251SAnup Patel 53*a72ab251SAnup Patelrequired: 54*a72ab251SAnup Patel - compatible 55*a72ab251SAnup Patel - mboxes 56*a72ab251SAnup Patel - riscv,sbi-mpxy-channel-id 57*a72ab251SAnup Patel 58*a72ab251SAnup PateladditionalProperties: false 59*a72ab251SAnup Patel 60*a72ab251SAnup Patelexamples: 61*a72ab251SAnup Patel - | 62*a72ab251SAnup Patel interrupt-controller { 63*a72ab251SAnup Patel compatible = "riscv,rpmi-mpxy-system-msi"; 64*a72ab251SAnup Patel mboxes = <&rpmi_shmem_mbox 0x2>; 65*a72ab251SAnup Patel riscv,sbi-mpxy-channel-id = <0x2000>; 66*a72ab251SAnup Patel }; 67*a72ab251SAnup Patel... 68