1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) 8 9maintainers: 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 12 13description: | 14 IA55 performs various interrupt controls including synchronization for the external 15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral 16 interrupts output by each IP. And it notifies the interrupt to the GIC 17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts 18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts 19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and 20 stand-up edge detection interrupts) 21 22properties: 23 compatible: 24 items: 25 - enum: 26 - renesas,r9a07g043u-irqc # RZ/G2UL 27 - renesas,r9a07g044-irqc # RZ/G2{L,LC} 28 - renesas,r9a07g054-irqc # RZ/V2L 29 - renesas,r9a08g045-irqc # RZ/G3S 30 - const: renesas,rzg2l-irqc 31 32 '#interrupt-cells': 33 description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the 34 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second 35 cell is used to specify the flag. 36 const: 2 37 38 '#address-cells': 39 const: 0 40 41 interrupt-controller: true 42 43 reg: 44 maxItems: 1 45 46 interrupts: 47 minItems: 45 48 items: 49 - description: NMI interrupt 50 - description: IRQ0 interrupt 51 - description: IRQ1 interrupt 52 - description: IRQ2 interrupt 53 - description: IRQ3 interrupt 54 - description: IRQ4 interrupt 55 - description: IRQ5 interrupt 56 - description: IRQ6 interrupt 57 - description: IRQ7 interrupt 58 - description: GPIO interrupt, TINT0 59 - description: GPIO interrupt, TINT1 60 - description: GPIO interrupt, TINT2 61 - description: GPIO interrupt, TINT3 62 - description: GPIO interrupt, TINT4 63 - description: GPIO interrupt, TINT5 64 - description: GPIO interrupt, TINT6 65 - description: GPIO interrupt, TINT7 66 - description: GPIO interrupt, TINT8 67 - description: GPIO interrupt, TINT9 68 - description: GPIO interrupt, TINT10 69 - description: GPIO interrupt, TINT11 70 - description: GPIO interrupt, TINT12 71 - description: GPIO interrupt, TINT13 72 - description: GPIO interrupt, TINT14 73 - description: GPIO interrupt, TINT15 74 - description: GPIO interrupt, TINT16 75 - description: GPIO interrupt, TINT17 76 - description: GPIO interrupt, TINT18 77 - description: GPIO interrupt, TINT19 78 - description: GPIO interrupt, TINT20 79 - description: GPIO interrupt, TINT21 80 - description: GPIO interrupt, TINT22 81 - description: GPIO interrupt, TINT23 82 - description: GPIO interrupt, TINT24 83 - description: GPIO interrupt, TINT25 84 - description: GPIO interrupt, TINT26 85 - description: GPIO interrupt, TINT27 86 - description: GPIO interrupt, TINT28 87 - description: GPIO interrupt, TINT29 88 - description: GPIO interrupt, TINT30 89 - description: GPIO interrupt, TINT31 90 - description: Bus error interrupt 91 - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt 92 - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt 93 - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt 94 - description: ECCRAM1 1bit error interrupt 95 - description: ECCRAM1 2bit error interrupt 96 - description: ECCRAM1 error overflow interrupt 97 98 interrupt-names: 99 minItems: 45 100 items: 101 - const: nmi 102 - const: irq0 103 - const: irq1 104 - const: irq2 105 - const: irq3 106 - const: irq4 107 - const: irq5 108 - const: irq6 109 - const: irq7 110 - const: tint0 111 - const: tint1 112 - const: tint2 113 - const: tint3 114 - const: tint4 115 - const: tint5 116 - const: tint6 117 - const: tint7 118 - const: tint8 119 - const: tint9 120 - const: tint10 121 - const: tint11 122 - const: tint12 123 - const: tint13 124 - const: tint14 125 - const: tint15 126 - const: tint16 127 - const: tint17 128 - const: tint18 129 - const: tint19 130 - const: tint20 131 - const: tint21 132 - const: tint22 133 - const: tint23 134 - const: tint24 135 - const: tint25 136 - const: tint26 137 - const: tint27 138 - const: tint28 139 - const: tint29 140 - const: tint30 141 - const: tint31 142 - const: bus-err 143 - const: ec7tie1-0 144 - const: ec7tie2-0 145 - const: ec7tiovf-0 146 - const: ec7tie1-1 147 - const: ec7tie2-1 148 - const: ec7tiovf-1 149 150 clocks: 151 maxItems: 2 152 153 clock-names: 154 items: 155 - const: clk 156 - const: pclk 157 158 power-domains: 159 maxItems: 1 160 161 resets: 162 maxItems: 1 163 164required: 165 - compatible 166 - '#interrupt-cells' 167 - '#address-cells' 168 - interrupt-controller 169 - reg 170 - interrupts 171 - interrupt-names 172 - clocks 173 - clock-names 174 - power-domains 175 - resets 176 177allOf: 178 - $ref: /schemas/interrupt-controller.yaml# 179 180 - if: 181 properties: 182 compatible: 183 contains: 184 enum: 185 - renesas,r9a08g045-irqc 186 then: 187 properties: 188 interrupts: 189 maxItems: 45 190 interrupt-names: 191 maxItems: 45 192 else: 193 properties: 194 interrupts: 195 minItems: 48 196 interrupt-names: 197 minItems: 48 198 199unevaluatedProperties: false 200 201examples: 202 - | 203 #include <dt-bindings/interrupt-controller/arm-gic.h> 204 #include <dt-bindings/clock/r9a07g044-cpg.h> 205 206 irqc: interrupt-controller@110a0000 { 207 compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; 208 reg = <0x110a0000 0x10000>; 209 #interrupt-cells = <2>; 210 #address-cells = <0>; 211 interrupt-controller; 212 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 258 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 260 interrupt-names = "nmi", 261 "irq0", "irq1", "irq2", "irq3", 262 "irq4", "irq5", "irq6", "irq7", 263 "tint0", "tint1", "tint2", "tint3", 264 "tint4", "tint5", "tint6", "tint7", 265 "tint8", "tint9", "tint10", "tint11", 266 "tint12", "tint13", "tint14", "tint15", 267 "tint16", "tint17", "tint18", "tint19", 268 "tint20", "tint21", "tint22", "tint23", 269 "tint24", "tint25", "tint26", "tint27", 270 "tint28", "tint29", "tint30", "tint31", 271 "bus-err", "ec7tie1-0", "ec7tie2-0", 272 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", 273 "ec7tiovf-1"; 274 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, 275 <&cpg CPG_MOD R9A07G044_IA55_PCLK>; 276 clock-names = "clk", "pclk"; 277 power-domains = <&cpg>; 278 resets = <&cpg R9A07G044_IA55_RESETN>; 279 }; 280