1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) 8 9maintainers: 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 12 13description: | 14 IA55 performs various interrupt controls including synchronization for the external 15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral 16 interrupts output by each IP. And it notifies the interrupt to the GIC 17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts 18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts 19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and 20 stand-up edge detection interrupts) 21 22properties: 23 compatible: 24 oneOf: 25 - items: 26 - enum: 27 - renesas,r9a07g043u-irqc # RZ/G2UL 28 - renesas,r9a07g044-irqc # RZ/G2{L,LC} 29 - renesas,r9a07g054-irqc # RZ/V2L 30 - renesas,r9a08g045-irqc # RZ/G3S 31 - const: renesas,rzg2l-irqc 32 33 - const: renesas,r9a07g043f-irqc # RZ/Five 34 35 '#interrupt-cells': 36 description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the 37 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second 38 cell is used to specify the flag. 39 const: 2 40 41 '#address-cells': 42 const: 0 43 44 interrupt-controller: true 45 46 reg: 47 maxItems: 1 48 49 interrupts: 50 minItems: 45 51 items: 52 - description: NMI interrupt 53 - description: IRQ0 interrupt 54 - description: IRQ1 interrupt 55 - description: IRQ2 interrupt 56 - description: IRQ3 interrupt 57 - description: IRQ4 interrupt 58 - description: IRQ5 interrupt 59 - description: IRQ6 interrupt 60 - description: IRQ7 interrupt 61 - description: GPIO interrupt, TINT0 62 - description: GPIO interrupt, TINT1 63 - description: GPIO interrupt, TINT2 64 - description: GPIO interrupt, TINT3 65 - description: GPIO interrupt, TINT4 66 - description: GPIO interrupt, TINT5 67 - description: GPIO interrupt, TINT6 68 - description: GPIO interrupt, TINT7 69 - description: GPIO interrupt, TINT8 70 - description: GPIO interrupt, TINT9 71 - description: GPIO interrupt, TINT10 72 - description: GPIO interrupt, TINT11 73 - description: GPIO interrupt, TINT12 74 - description: GPIO interrupt, TINT13 75 - description: GPIO interrupt, TINT14 76 - description: GPIO interrupt, TINT15 77 - description: GPIO interrupt, TINT16 78 - description: GPIO interrupt, TINT17 79 - description: GPIO interrupt, TINT18 80 - description: GPIO interrupt, TINT19 81 - description: GPIO interrupt, TINT20 82 - description: GPIO interrupt, TINT21 83 - description: GPIO interrupt, TINT22 84 - description: GPIO interrupt, TINT23 85 - description: GPIO interrupt, TINT24 86 - description: GPIO interrupt, TINT25 87 - description: GPIO interrupt, TINT26 88 - description: GPIO interrupt, TINT27 89 - description: GPIO interrupt, TINT28 90 - description: GPIO interrupt, TINT29 91 - description: GPIO interrupt, TINT30 92 - description: GPIO interrupt, TINT31 93 - description: Bus error interrupt 94 - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt 95 - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt 96 - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt 97 - description: ECCRAM1 1bit error interrupt 98 - description: ECCRAM1 2bit error interrupt 99 - description: ECCRAM1 error overflow interrupt 100 101 interrupt-names: 102 minItems: 45 103 items: 104 - const: nmi 105 - const: irq0 106 - const: irq1 107 - const: irq2 108 - const: irq3 109 - const: irq4 110 - const: irq5 111 - const: irq6 112 - const: irq7 113 - const: tint0 114 - const: tint1 115 - const: tint2 116 - const: tint3 117 - const: tint4 118 - const: tint5 119 - const: tint6 120 - const: tint7 121 - const: tint8 122 - const: tint9 123 - const: tint10 124 - const: tint11 125 - const: tint12 126 - const: tint13 127 - const: tint14 128 - const: tint15 129 - const: tint16 130 - const: tint17 131 - const: tint18 132 - const: tint19 133 - const: tint20 134 - const: tint21 135 - const: tint22 136 - const: tint23 137 - const: tint24 138 - const: tint25 139 - const: tint26 140 - const: tint27 141 - const: tint28 142 - const: tint29 143 - const: tint30 144 - const: tint31 145 - const: bus-err 146 - const: ec7tie1-0 147 - const: ec7tie2-0 148 - const: ec7tiovf-0 149 - const: ec7tie1-1 150 - const: ec7tie2-1 151 - const: ec7tiovf-1 152 153 clocks: 154 maxItems: 2 155 156 clock-names: 157 items: 158 - const: clk 159 - const: pclk 160 161 power-domains: 162 maxItems: 1 163 164 resets: 165 maxItems: 1 166 167required: 168 - compatible 169 - '#interrupt-cells' 170 - '#address-cells' 171 - interrupt-controller 172 - reg 173 - interrupts 174 - interrupt-names 175 - clocks 176 - clock-names 177 - power-domains 178 - resets 179 180allOf: 181 - $ref: /schemas/interrupt-controller.yaml# 182 183 - if: 184 properties: 185 compatible: 186 contains: 187 enum: 188 - renesas,r9a08g045-irqc 189 then: 190 properties: 191 interrupts: 192 maxItems: 45 193 interrupt-names: 194 maxItems: 45 195 else: 196 properties: 197 interrupts: 198 minItems: 48 199 interrupt-names: 200 minItems: 48 201 202unevaluatedProperties: false 203 204examples: 205 - | 206 #include <dt-bindings/interrupt-controller/arm-gic.h> 207 #include <dt-bindings/clock/r9a07g044-cpg.h> 208 209 irqc: interrupt-controller@110a0000 { 210 compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; 211 reg = <0x110a0000 0x10000>; 212 #interrupt-cells = <2>; 213 #address-cells = <0>; 214 interrupt-controller; 215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 258 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 261 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 262 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 263 interrupt-names = "nmi", 264 "irq0", "irq1", "irq2", "irq3", 265 "irq4", "irq5", "irq6", "irq7", 266 "tint0", "tint1", "tint2", "tint3", 267 "tint4", "tint5", "tint6", "tint7", 268 "tint8", "tint9", "tint10", "tint11", 269 "tint12", "tint13", "tint14", "tint15", 270 "tint16", "tint17", "tint18", "tint19", 271 "tint20", "tint21", "tint22", "tint23", 272 "tint24", "tint25", "tint26", "tint27", 273 "tint28", "tint29", "tint30", "tint31", 274 "bus-err", "ec7tie1-0", "ec7tie2-0", 275 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", 276 "ec7tiovf-1"; 277 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, 278 <&cpg CPG_MOD R9A07G044_IA55_PCLK>; 279 clock-names = "clk", "pclk"; 280 power-domains = <&cpg>; 281 resets = <&cpg R9A07G044_IA55_RESETN>; 282 }; 283