xref: /linux/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PDC interrupt controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14  Power Domain Controller (PDC) that is on always-on domain. In addition to
15  providing power control for the power domains, the hardware also has an
16  interrupt controller that can be used to help detect edge low interrupts as
17  well detect interrupts when the GIC is non-operational.
18
19  GIC is parent interrupt controller at the highest level. Platform interrupt
20  controller PDC is next in hierarchy, followed by others. Drivers requiring
21  wakeup capabilities of their device interrupts routed through the PDC, must
22  specify PDC as their interrupt controller and request the PDC port associated
23  with the GIC interrupt. See example below.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,qdu1000-pdc
30          - qcom,sa8255p-pdc
31          - qcom,sa8775p-pdc
32          - qcom,sar2130p-pdc
33          - qcom,sc7180-pdc
34          - qcom,sc7280-pdc
35          - qcom,sc8180x-pdc
36          - qcom,sc8280xp-pdc
37          - qcom,sdm670-pdc
38          - qcom,sdm845-pdc
39          - qcom,sdx55-pdc
40          - qcom,sdx65-pdc
41          - qcom,sdx75-pdc
42          - qcom,sm4450-pdc
43          - qcom,sm6350-pdc
44          - qcom,sm8150-pdc
45          - qcom,sm8250-pdc
46          - qcom,sm8350-pdc
47          - qcom,sm8450-pdc
48          - qcom,sm8550-pdc
49          - qcom,sm8650-pdc
50          - qcom,x1e80100-pdc
51      - const: qcom,pdc
52
53  reg:
54    minItems: 1
55    items:
56      - description: PDC base register region
57      - description: Edge or Level config register for SPI interrupts
58
59  '#interrupt-cells':
60    const: 2
61
62  interrupt-controller: true
63
64  qcom,pdc-ranges:
65    $ref: /schemas/types.yaml#/definitions/uint32-matrix
66    minItems: 1
67    maxItems: 128 # no hard limit
68    items:
69      items:
70        - description: starting PDC port
71        - description: GIC hwirq number for the PDC port
72        - description: number of interrupts in sequence
73    description: |
74      Specifies the PDC pin offset and the number of PDC ports.
75      The tuples indicates the valid mapping of valid PDC ports
76      and their hwirq mapping.
77
78required:
79  - compatible
80  - reg
81  - '#interrupt-cells'
82  - interrupt-controller
83  - qcom,pdc-ranges
84
85additionalProperties: false
86
87examples:
88  - |
89    #include <dt-bindings/interrupt-controller/irq.h>
90
91    pdc: interrupt-controller@b220000 {
92        compatible = "qcom,sdm845-pdc", "qcom,pdc";
93        reg = <0xb220000 0x30000>;
94        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
95        #interrupt-cells = <2>;
96        interrupt-parent = <&intc>;
97        interrupt-controller;
98    };
99
100    wake-device {
101        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
102    };
103