xref: /linux/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml (revision 7a5f1cd22d47f8ca4b760b6334378ae42c1bd24b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PDC interrupt controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14  Power Domain Controller (PDC) that is on always-on domain. In addition to
15  providing power control for the power domains, the hardware also has an
16  interrupt controller that can be used to help detect edge low interrupts as
17  well detect interrupts when the GIC is non-operational.
18
19  GIC is parent interrupt controller at the highest level. Platform interrupt
20  controller PDC is next in hierarchy, followed by others. Drivers requiring
21  wakeup capabilities of their device interrupts routed through the PDC, must
22  specify PDC as their interrupt controller and request the PDC port associated
23  with the GIC interrupt. See example below.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,eliza-pdc
30          - qcom,glymur-pdc
31          - qcom,hawi-pdc
32          - qcom,kaanapali-pdc
33          - qcom,milos-pdc
34          - qcom,qcs615-pdc
35          - qcom,qcs8300-pdc
36          - qcom,qdu1000-pdc
37          - qcom,sa8255p-pdc
38          - qcom,sa8775p-pdc
39          - qcom,sar2130p-pdc
40          - qcom,sc7180-pdc
41          - qcom,sc7280-pdc
42          - qcom,sc8180x-pdc
43          - qcom,sc8280xp-pdc
44          - qcom,sdm670-pdc
45          - qcom,sdm845-pdc
46          - qcom,sdx55-pdc
47          - qcom,sdx65-pdc
48          - qcom,sdx75-pdc
49          - qcom,sm4450-pdc
50          - qcom,sm6350-pdc
51          - qcom,sm8150-pdc
52          - qcom,sm8250-pdc
53          - qcom,sm8350-pdc
54          - qcom,sm8450-pdc
55          - qcom,sm8550-pdc
56          - qcom,sm8650-pdc
57          - qcom,sm8750-pdc
58          - qcom,x1e80100-pdc
59      - const: qcom,pdc
60
61  reg:
62    minItems: 1
63    items:
64      - description: PDC base register region
65      - description: Edge or Level config register for SPI interrupts
66
67  '#interrupt-cells':
68    const: 2
69
70  interrupt-controller: true
71
72  qcom,pdc-ranges:
73    $ref: /schemas/types.yaml#/definitions/uint32-matrix
74    minItems: 1
75    maxItems: 128 # no hard limit
76    items:
77      items:
78        - description: starting PDC port
79        - description: GIC hwirq number for the PDC port
80        - description: number of interrupts in sequence
81    description: |
82      Specifies the PDC pin offset and the number of PDC ports.
83      The tuples indicates the valid mapping of valid PDC ports
84      and their hwirq mapping.
85
86required:
87  - compatible
88  - reg
89  - '#interrupt-cells'
90  - interrupt-controller
91  - qcom,pdc-ranges
92
93additionalProperties: false
94
95examples:
96  - |
97    #include <dt-bindings/interrupt-controller/irq.h>
98
99    pdc: interrupt-controller@b220000 {
100        compatible = "qcom,sdm845-pdc", "qcom,pdc";
101        reg = <0xb220000 0x30000>;
102        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
103        #interrupt-cells = <2>;
104        interrupt-parent = <&intc>;
105        interrupt-controller;
106    };
107
108    wake-device {
109        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
110    };
111