xref: /linux/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml (revision 5d7f3375cd574fc83f0cd30839b21455c0e79ae2) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PDC interrupt controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14  Power Domain Controller (PDC) that is on always-on domain. In addition to
15  providing power control for the power domains, the hardware also has an
16  interrupt controller that can be used to help detect edge low interrupts as
17  well detect interrupts when the GIC is non-operational.
18
19  GIC is parent interrupt controller at the highest level. Platform interrupt
20  controller PDC is next in hierarchy, followed by others. Drivers requiring
21  wakeup capabilities of their device interrupts routed through the PDC, must
22  specify PDC as their interrupt controller and request the PDC port associated
23  with the GIC interrupt. See example below.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,eliza-pdc
30          - qcom,glymur-pdc
31          - qcom,hawi-pdc
32          - qcom,kaanapali-pdc
33          - qcom,maili-pdc
34          - qcom,milos-pdc
35          - qcom,nord-pdc
36          - qcom,qcs615-pdc
37          - qcom,qcs8300-pdc
38          - qcom,qdu1000-pdc
39          - qcom,sa8255p-pdc
40          - qcom,sa8775p-pdc
41          - qcom,sar2130p-pdc
42          - qcom,sc7180-pdc
43          - qcom,sc7280-pdc
44          - qcom,sc8180x-pdc
45          - qcom,sc8280xp-pdc
46          - qcom,sdm670-pdc
47          - qcom,sdm845-pdc
48          - qcom,sdx55-pdc
49          - qcom,sdx65-pdc
50          - qcom,sdx75-pdc
51          - qcom,sm4450-pdc
52          - qcom,sm6350-pdc
53          - qcom,sm8150-pdc
54          - qcom,sm8250-pdc
55          - qcom,sm8350-pdc
56          - qcom,sm8450-pdc
57          - qcom,sm8550-pdc
58          - qcom,sm8650-pdc
59          - qcom,sm8750-pdc
60          - qcom,x1e80100-pdc
61          - qcom,x1p42100-pdc
62      - const: qcom,pdc
63
64  reg:
65    minItems: 1
66    items:
67      - description: PDC base register region
68      - description: Edge or Level config register for SPI interrupts
69
70  '#interrupt-cells':
71    const: 2
72
73  interrupt-controller: true
74
75  qcom,pdc-ranges:
76    $ref: /schemas/types.yaml#/definitions/uint32-matrix
77    minItems: 1
78    maxItems: 128 # no hard limit
79    items:
80      items:
81        - description: starting PDC port
82        - description: GIC hwirq number for the PDC port
83        - description: number of interrupts in sequence
84    description: |
85      Specifies the PDC pin offset and the number of PDC ports.
86      The tuples indicates the valid mapping of valid PDC ports
87      and their hwirq mapping.
88
89required:
90  - compatible
91  - reg
92  - '#interrupt-cells'
93  - interrupt-controller
94  - qcom,pdc-ranges
95
96additionalProperties: false
97
98examples:
99  - |
100    #include <dt-bindings/interrupt-controller/irq.h>
101
102    pdc: interrupt-controller@b220000 {
103        compatible = "qcom,sdm845-pdc", "qcom,pdc";
104        reg = <0xb220000 0x30000>;
105        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
106        #interrupt-cells = <2>;
107        interrupt-parent = <&intc>;
108        interrupt-controller;
109    };
110
111    wake-device {
112        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
113    };
114