xref: /linux/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml (revision 527a0f2bdcfe77fce22f006b97e42e4da3137c86) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PDC interrupt controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14  Power Domain Controller (PDC) that is on always-on domain. In addition to
15  providing power control for the power domains, the hardware also has an
16  interrupt controller that can be used to help detect edge low interrupts as
17  well detect interrupts when the GIC is non-operational.
18
19  GIC is parent interrupt controller at the highest level. Platform interrupt
20  controller PDC is next in hierarchy, followed by others. Drivers requiring
21  wakeup capabilities of their device interrupts routed through the PDC, must
22  specify PDC as their interrupt controller and request the PDC port associated
23  with the GIC interrupt. See example below.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,qdu1000-pdc
30          - qcom,sa8775p-pdc
31          - qcom,sc7180-pdc
32          - qcom,sc7280-pdc
33          - qcom,sc8180x-pdc
34          - qcom,sc8280xp-pdc
35          - qcom,sdm670-pdc
36          - qcom,sdm845-pdc
37          - qcom,sdx55-pdc
38          - qcom,sdx65-pdc
39          - qcom,sdx75-pdc
40          - qcom,sm4450-pdc
41          - qcom,sm6350-pdc
42          - qcom,sm8150-pdc
43          - qcom,sm8250-pdc
44          - qcom,sm8350-pdc
45          - qcom,sm8450-pdc
46          - qcom,sm8550-pdc
47          - qcom,sm8650-pdc
48          - qcom,x1e80100-pdc
49      - const: qcom,pdc
50
51  reg:
52    minItems: 1
53    items:
54      - description: PDC base register region
55      - description: Edge or Level config register for SPI interrupts
56
57  '#interrupt-cells':
58    const: 2
59
60  interrupt-controller: true
61
62  qcom,pdc-ranges:
63    $ref: /schemas/types.yaml#/definitions/uint32-matrix
64    minItems: 1
65    maxItems: 128 # no hard limit
66    items:
67      items:
68        - description: starting PDC port
69        - description: GIC hwirq number for the PDC port
70        - description: number of interrupts in sequence
71    description: |
72      Specifies the PDC pin offset and the number of PDC ports.
73      The tuples indicates the valid mapping of valid PDC ports
74      and their hwirq mapping.
75
76required:
77  - compatible
78  - reg
79  - '#interrupt-cells'
80  - interrupt-controller
81  - qcom,pdc-ranges
82
83additionalProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/interrupt-controller/irq.h>
88
89    pdc: interrupt-controller@b220000 {
90        compatible = "qcom,sdm845-pdc", "qcom,pdc";
91        reg = <0xb220000 0x30000>;
92        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
93        #interrupt-cells = <2>;
94        interrupt-parent = <&intc>;
95        interrupt-controller;
96    };
97
98    wake-device {
99        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
100    };
101