1Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 2 3The MISC interrupt controller is a secondary controller for lower priority 4interrupt. 5 6Required Properties: 7- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or 8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" 9- reg: Base address and size of the controllers memory area 10- interrupt-parent: phandle of the parent interrupt controller. 11- interrupts: Interrupt specifier for the controllers interrupt. 12- interrupt-controller : Identifies the node as an interrupt controller 13- #interrupt-cells : Specifies the number of cells needed to encode interrupt 14 source, should be 1 15 16Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, 17use ar7240 for all other SoCs. 18 19Please refer to interrupts.txt in this directory for details of the common 20Interrupt Controllers bindings used by client devices. 21 22Example: 23 24 interrupt-controller@18060010 { 25 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; 26 reg = <0x18060010 0x4>; 27 28 interrupt-parent = <&cpuintc>; 29 interrupts = <6>; 30 31 interrupt-controller; 32 #interrupt-cells = <1>; 33 }; 34 35Another example: 36 37 interrupt-controller@18060010 { 38 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; 39 reg = <0x18060010 0x4>; 40 41 interrupt-parent = <&cpuintc>; 42 interrupts = <6>; 43 44 interrupt-controller; 45 #interrupt-cells = <1>; 46 }; 47