1*f3ce2e12SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f3ce2e12SRob Herring (Arm)%YAML 1.2 3*f3ce2e12SRob Herring (Arm)--- 4*f3ce2e12SRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml# 5*f3ce2e12SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f3ce2e12SRob Herring (Arm) 7*f3ce2e12SRob Herring (Arm)title: Qualcomm Atheros ath79 CPU interrupt controller 8*f3ce2e12SRob Herring (Arm) 9*f3ce2e12SRob Herring (Arm)maintainers: 10*f3ce2e12SRob Herring (Arm) - Alban Bedel <albeu@free.fr> 11*f3ce2e12SRob Herring (Arm) 12*f3ce2e12SRob Herring (Arm)description: 13*f3ce2e12SRob Herring (Arm) On most SoC the IRQ controller need to flush the DDR FIFO before running the 14*f3ce2e12SRob Herring (Arm) interrupt handler of some devices. This is configured using the 15*f3ce2e12SRob Herring (Arm) qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. 16*f3ce2e12SRob Herring (Arm) 17*f3ce2e12SRob Herring (Arm)properties: 18*f3ce2e12SRob Herring (Arm) compatible: 19*f3ce2e12SRob Herring (Arm) oneOf: 20*f3ce2e12SRob Herring (Arm) - items: 21*f3ce2e12SRob Herring (Arm) - const: qca,ar9132-cpu-intc 22*f3ce2e12SRob Herring (Arm) - const: qca,ar7100-cpu-intc 23*f3ce2e12SRob Herring (Arm) - items: 24*f3ce2e12SRob Herring (Arm) - const: qca,ar7100-cpu-intc 25*f3ce2e12SRob Herring (Arm) 26*f3ce2e12SRob Herring (Arm) interrupt-controller: true 27*f3ce2e12SRob Herring (Arm) 28*f3ce2e12SRob Herring (Arm) '#interrupt-cells': 29*f3ce2e12SRob Herring (Arm) const: 1 30*f3ce2e12SRob Herring (Arm) 31*f3ce2e12SRob Herring (Arm) qca,ddr-wb-channel-interrupts: 32*f3ce2e12SRob Herring (Arm) description: List of interrupts needing a write buffer flush 33*f3ce2e12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32-array 34*f3ce2e12SRob Herring (Arm) 35*f3ce2e12SRob Herring (Arm) qca,ddr-wb-channels: 36*f3ce2e12SRob Herring (Arm) description: List of write buffer channel phandles for each interrupt 37*f3ce2e12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/phandle-array 38*f3ce2e12SRob Herring (Arm) 39*f3ce2e12SRob Herring (Arm)required: 40*f3ce2e12SRob Herring (Arm) - compatible 41*f3ce2e12SRob Herring (Arm) - interrupt-controller 42*f3ce2e12SRob Herring (Arm) - '#interrupt-cells' 43*f3ce2e12SRob Herring (Arm) 44*f3ce2e12SRob Herring (Arm)additionalProperties: false 45*f3ce2e12SRob Herring (Arm) 46*f3ce2e12SRob Herring (Arm)examples: 47*f3ce2e12SRob Herring (Arm) - | 48*f3ce2e12SRob Herring (Arm) interrupt-controller { 49*f3ce2e12SRob Herring (Arm) compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 50*f3ce2e12SRob Herring (Arm) 51*f3ce2e12SRob Herring (Arm) interrupt-controller; 52*f3ce2e12SRob Herring (Arm) #interrupt-cells = <1>; 53*f3ce2e12SRob Herring (Arm) 54*f3ce2e12SRob Herring (Arm) qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 55*f3ce2e12SRob Herring (Arm) qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 56*f3ce2e12SRob Herring (Arm) <&ddr_ctrl 0>, <&ddr_ctrl 1>; 57*f3ce2e12SRob Herring (Arm) }; 58*f3ce2e12SRob Herring (Arm) 59*f3ce2e12SRob Herring (Arm) ddr_ctrl: memory-controller { 60*f3ce2e12SRob Herring (Arm) #qca,ddr-wb-channel-cells = <1>; 61*f3ce2e12SRob Herring (Arm) }; 62