1*9b54470aSStafford HorneOpen Multi-Processor Interrupt Controller 2*9b54470aSStafford Horne 3*9b54470aSStafford HorneRequired properties: 4*9b54470aSStafford Horne 5*9b54470aSStafford Horne- compatible : This should be "openrisc,ompic" 6*9b54470aSStafford Horne- reg : Specifies base physical address and size of the register space. The 7*9b54470aSStafford Horne size is based on the number of cores the controller has been configured 8*9b54470aSStafford Horne to handle, this should be set to 8 bytes per cpu core. 9*9b54470aSStafford Horne- interrupt-controller : Identifies the node as an interrupt controller. 10*9b54470aSStafford Horne- #interrupt-cells : This should be set to 0 as this will not be an irq 11*9b54470aSStafford Horne parent. 12*9b54470aSStafford Horne- interrupts : Specifies the interrupt line to which the ompic is wired. 13*9b54470aSStafford Horne 14*9b54470aSStafford HorneExample: 15*9b54470aSStafford Horne 16*9b54470aSStafford Horneompic: interrupt-controller@98000000 { 17*9b54470aSStafford Horne compatible = "openrisc,ompic"; 18*9b54470aSStafford Horne reg = <0x98000000 16>; 19*9b54470aSStafford Horne interrupt-controller; 20*9b54470aSStafford Horne #interrupt-cells = <0>; 21*9b54470aSStafford Horne interrupts = <1>; 22*9b54470aSStafford Horne}; 23