1* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers 2 3Required properties: 4- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". 5- reg: should contain IC registers location and length. 6- interrupt-controller: identifies the node as an interrupt controller. 7- #interrupt-cells: the number of cells to define an interrupt, should be 2. 8 The first cell is the IRQ number, the second cell is used to specify 9 one of the supported IRQ types: 10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, 11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, 12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, 13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive. 14 Reset value is IRQ_TYPE_LEVEL_LOW. 15 16Optional properties: 17- interrupts: empty for MIC interrupt controller, cascaded MIC 18 hardware interrupts for SIC1 and SIC2 19 20Examples: 21 22 /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ 23 mic: interrupt-controller@40008000 { 24 compatible = "nxp,lpc3220-mic"; 25 reg = <0x40008000 0x4000>; 26 interrupt-controller; 27 #interrupt-cells = <2>; 28 }; 29 30 sic1: interrupt-controller@4000c000 { 31 compatible = "nxp,lpc3220-sic"; 32 reg = <0x4000c000 0x4000>; 33 interrupt-controller; 34 #interrupt-cells = <2>; 35 36 interrupt-parent = <&mic>; 37 interrupts = <0 IRQ_TYPE_LEVEL_LOW>, 38 <30 IRQ_TYPE_LEVEL_LOW>; 39 }; 40 41 sic2: interrupt-controller@40010000 { 42 compatible = "nxp,lpc3220-sic"; 43 reg = <0x40010000 0x4000>; 44 interrupt-controller; 45 #interrupt-cells = <2>; 46 47 interrupt-parent = <&mic>; 48 interrupts = <1 IRQ_TYPE_LEVEL_LOW>, 49 <31 IRQ_TYPE_LEVEL_LOW>; 50 }; 51 52 /* ADC */ 53 adc@40048000 { 54 compatible = "nxp,lpc3220-adc"; 55 reg = <0x40048000 0x1000>; 56 interrupt-parent = <&sic1>; 57 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 58 }; 59