1a8ca1b28SThierry RedingNVIDIA Legacy Interrupt Controller 2a8ca1b28SThierry Reding 3a8ca1b28SThierry RedingAll Tegra SoCs contain a legacy interrupt controller that routes 4a8ca1b28SThierry Redinginterrupts to the GIC, and also serves as a wakeup source. It is also 5a8ca1b28SThierry Redingreferred to as "ictlr", hence the name of the binding. 6a8ca1b28SThierry Reding 7a8ca1b28SThierry RedingThe HW block exposes a number of interrupt controllers, each 8a8ca1b28SThierry Redingimplementing a set of 32 interrupts. 9a8ca1b28SThierry Reding 10a8ca1b28SThierry RedingRequired properties: 11a8ca1b28SThierry Reding 12a8ca1b28SThierry Reding- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on 13a8ca1b28SThierry Reding subsequent SoCs remained backwards-compatible with Tegra30, so on 14a8ca1b28SThierry Reding Tegra generations later than Tegra30 the compatible value should 15a8ca1b28SThierry Reding include "nvidia,tegra30-ictlr". 16a8ca1b28SThierry Reding- reg : Specifies base physical address and size of the registers. 17a8ca1b28SThierry Reding Each controller must be described separately (Tegra20 has 4 of them, 18*a47c9b39SJonathan Neuschäfer whereas Tegra30 and later have 5). 19a8ca1b28SThierry Reding- interrupt-controller : Identifies the node as an interrupt controller. 20a8ca1b28SThierry Reding- #interrupt-cells : Specifies the number of cells needed to encode an 21a8ca1b28SThierry Reding interrupt source. The value must be 3. 22a8ca1b28SThierry Reding 23a8ca1b28SThierry RedingNotes: 24a8ca1b28SThierry Reding 25a8ca1b28SThierry Reding- Because this HW ultimately routes interrupts to the GIC, the 26a8ca1b28SThierry Reding interrupt specifier must be that of the GIC. 27a8ca1b28SThierry Reding- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs 28a8ca1b28SThierry Reding are explicitly forbidden. 29a8ca1b28SThierry Reding 30a8ca1b28SThierry RedingExample: 31a8ca1b28SThierry Reding 32a8ca1b28SThierry Reding ictlr: interrupt-controller@60004000 { 33a8ca1b28SThierry Reding compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr"; 34a8ca1b28SThierry Reding reg = <0x60004000 64>, 35a8ca1b28SThierry Reding <0x60004100 64>, 36a8ca1b28SThierry Reding <0x60004200 64>, 37a8ca1b28SThierry Reding <0x60004300 64>; 38a8ca1b28SThierry Reding interrupt-controller; 39a8ca1b28SThierry Reding #interrupt-cells = <3>; 40a8ca1b28SThierry Reding interrupt-parent = <&intc>; 41a8ca1b28SThierry Reding }; 42