1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MIPS Global Interrupt Controller 8 9maintainers: 10 - Paul Burton <paulburton@kernel.org> 11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de> 12 13description: | 14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. 15 It also supports local (per-processor) interrupts and software-generated 16 interrupts which can be used as IPIs. The GIC also includes a free-running 17 global timer, per-CPU count/compare timers, and a watchdog. 18 19properties: 20 compatible: 21 const: mti,gic 22 23 "#interrupt-cells": 24 const: 3 25 description: | 26 The 1st cell is the type of interrupt: local or shared defined in the 27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the 28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up 29 the IRQ trigger modes, which are defined in the file 30 'dt-bindings/interrupt-controller/irq.h'. 31 32 reg: 33 description: | 34 Base address and length of the GIC registers space. If not present, 35 the base address reported by the hardware GCR_GIC_BASE will be used. 36 maxItems: 1 37 38 interrupt-controller: true 39 40 mti,reserved-cpu-vectors: 41 description: | 42 Specifies the list of CPU interrupt vectors to which the GIC may not 43 route interrupts. This property is ignored if the CPU is started in EIC 44 mode. 45 allOf: 46 - $ref: /schemas/types.yaml#definitions/uint32-array 47 - minItems: 1 48 maxItems: 6 49 uniqueItems: true 50 items: 51 minimum: 2 52 maximum: 7 53 54 mti,reserved-ipi-vectors: 55 description: | 56 Specifies the range of GIC interrupts that are reserved for IPIs. 57 It accepts two values: the 1st is the starting interrupt and the 2nd is 58 the size of the reserved range. If not specified, the driver will 59 allocate the last (2 * number of VPEs in the system). 60 allOf: 61 - $ref: /schemas/types.yaml#definitions/uint32-array 62 - items: 63 - minimum: 0 64 maximum: 254 65 - minimum: 2 66 maximum: 254 67 68 timer: 69 type: object 70 description: | 71 MIPS GIC includes a free-running global timer, per-CPU count/compare 72 timers, and a watchdog. Currently only the GIC Timer is supported. 73 properties: 74 compatible: 75 const: mti,gic-timer 76 77 interrupts: 78 description: | 79 Interrupt for the GIC local timer, so normally it's suppose to be of 80 <GIC_LOCAL X IRQ_TYPE_NONE> format. 81 maxItems: 1 82 83 clocks: 84 maxItems: 1 85 86 clock-frequency: true 87 88 required: 89 - compatible 90 - interrupts 91 92 oneOf: 93 - required: 94 - clocks 95 - required: 96 - clock-frequency 97 98 additionalProperties: false 99 100unevaluatedProperties: false 101 102required: 103 - compatible 104 - "#interrupt-cells" 105 - interrupt-controller 106 107examples: 108 - | 109 #include <dt-bindings/interrupt-controller/mips-gic.h> 110 #include <dt-bindings/interrupt-controller/irq.h> 111 112 interrupt-controller@1bdc0000 { 113 compatible = "mti,gic"; 114 reg = <0x1bdc0000 0x20000>; 115 interrupt-controller; 116 #interrupt-cells = <3>; 117 mti,reserved-cpu-vectors = <7>; 118 mti,reserved-ipi-vectors = <40 8>; 119 120 timer { 121 compatible = "mti,gic-timer"; 122 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 123 clock-frequency = <50000000>; 124 }; 125 }; 126 - | 127 #include <dt-bindings/interrupt-controller/mips-gic.h> 128 #include <dt-bindings/interrupt-controller/irq.h> 129 130 interrupt-controller@1bdc0000 { 131 compatible = "mti,gic"; 132 reg = <0x1bdc0000 0x20000>; 133 interrupt-controller; 134 #interrupt-cells = <3>; 135 136 timer { 137 compatible = "mti,gic-timer"; 138 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 139 clocks = <&cpu_pll>; 140 }; 141 }; 142 - | 143 interrupt-controller { 144 compatible = "mti,gic"; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 }; 148... 149