1e4fd9707SSerge Semin# SPDX-License-Identifier: GPL-2.0-only 2e4fd9707SSerge Semin%YAML 1.2 3e4fd9707SSerge Semin--- 4e4fd9707SSerge Semin$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# 5e4fd9707SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 6e4fd9707SSerge Semin 7e4fd9707SSerge Semintitle: MIPS Global Interrupt Controller 8e4fd9707SSerge Semin 9e4fd9707SSerge Seminmaintainers: 10e4fd9707SSerge Semin - Paul Burton <paulburton@kernel.org> 11e4fd9707SSerge Semin - Thomas Bogendoerfer <tsbogend@alpha.franken.de> 12e4fd9707SSerge Semin 13e4fd9707SSerge Semindescription: | 14e4fd9707SSerge Semin The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. 15e4fd9707SSerge Semin It also supports local (per-processor) interrupts and software-generated 16e4fd9707SSerge Semin interrupts which can be used as IPIs. The GIC also includes a free-running 17e4fd9707SSerge Semin global timer, per-CPU count/compare timers, and a watchdog. 18e4fd9707SSerge Semin 19e4fd9707SSerge Seminproperties: 20e4fd9707SSerge Semin compatible: 21e4fd9707SSerge Semin const: mti,gic 22e4fd9707SSerge Semin 23e4fd9707SSerge Semin "#interrupt-cells": 24e4fd9707SSerge Semin const: 3 25e4fd9707SSerge Semin description: | 26e4fd9707SSerge Semin The 1st cell is the type of interrupt: local or shared defined in the 27e4fd9707SSerge Semin file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the 28e4fd9707SSerge Semin GIC interrupt number. The 3d cell encodes the interrupt flags setting up 29e4fd9707SSerge Semin the IRQ trigger modes, which are defined in the file 30e4fd9707SSerge Semin 'dt-bindings/interrupt-controller/irq.h'. 31e4fd9707SSerge Semin 32e4fd9707SSerge Semin reg: 33e4fd9707SSerge Semin description: | 34e4fd9707SSerge Semin Base address and length of the GIC registers space. If not present, 35e4fd9707SSerge Semin the base address reported by the hardware GCR_GIC_BASE will be used. 36e4fd9707SSerge Semin maxItems: 1 37e4fd9707SSerge Semin 38e4fd9707SSerge Semin interrupt-controller: true 39e4fd9707SSerge Semin 40e4fd9707SSerge Semin mti,reserved-cpu-vectors: 41e4fd9707SSerge Semin description: | 42e4fd9707SSerge Semin Specifies the list of CPU interrupt vectors to which the GIC may not 43e4fd9707SSerge Semin route interrupts. This property is ignored if the CPU is started in EIC 44e4fd9707SSerge Semin mode. 455f0b06daSRob Herring $ref: /schemas/types.yaml#definitions/uint32-array 465f0b06daSRob Herring minItems: 1 47e4fd9707SSerge Semin maxItems: 6 48e4fd9707SSerge Semin uniqueItems: true 49e4fd9707SSerge Semin items: 50e4fd9707SSerge Semin minimum: 2 51e4fd9707SSerge Semin maximum: 7 52e4fd9707SSerge Semin 53e4fd9707SSerge Semin mti,reserved-ipi-vectors: 54e4fd9707SSerge Semin description: | 55e4fd9707SSerge Semin Specifies the range of GIC interrupts that are reserved for IPIs. 56e4fd9707SSerge Semin It accepts two values: the 1st is the starting interrupt and the 2nd is 57e4fd9707SSerge Semin the size of the reserved range. If not specified, the driver will 58e4fd9707SSerge Semin allocate the last (2 * number of VPEs in the system). 595f0b06daSRob Herring $ref: /schemas/types.yaml#definitions/uint32-array 605f0b06daSRob Herring items: 61e4fd9707SSerge Semin - minimum: 0 62e4fd9707SSerge Semin maximum: 254 63e4fd9707SSerge Semin - minimum: 2 64e4fd9707SSerge Semin maximum: 254 65e4fd9707SSerge Semin 66e4fd9707SSerge Semin timer: 67e4fd9707SSerge Semin type: object 68e4fd9707SSerge Semin description: | 69e4fd9707SSerge Semin MIPS GIC includes a free-running global timer, per-CPU count/compare 70e4fd9707SSerge Semin timers, and a watchdog. Currently only the GIC Timer is supported. 71e4fd9707SSerge Semin properties: 72e4fd9707SSerge Semin compatible: 73e4fd9707SSerge Semin const: mti,gic-timer 74e4fd9707SSerge Semin 75e4fd9707SSerge Semin interrupts: 76e4fd9707SSerge Semin description: | 77e4fd9707SSerge Semin Interrupt for the GIC local timer, so normally it's suppose to be of 78e4fd9707SSerge Semin <GIC_LOCAL X IRQ_TYPE_NONE> format. 79e4fd9707SSerge Semin maxItems: 1 80e4fd9707SSerge Semin 81e4fd9707SSerge Semin clocks: 82e4fd9707SSerge Semin maxItems: 1 83e4fd9707SSerge Semin 84e4fd9707SSerge Semin clock-frequency: true 85e4fd9707SSerge Semin 86e4fd9707SSerge Semin required: 87e4fd9707SSerge Semin - compatible 88e4fd9707SSerge Semin - interrupts 89e4fd9707SSerge Semin 90e4fd9707SSerge Semin oneOf: 91e4fd9707SSerge Semin - required: 92e4fd9707SSerge Semin - clocks 93e4fd9707SSerge Semin - required: 94e4fd9707SSerge Semin - clock-frequency 95e4fd9707SSerge Semin 96e4fd9707SSerge Semin additionalProperties: false 97e4fd9707SSerge Semin 98*4828556dSRob HerringadditionalProperties: false 99e4fd9707SSerge Semin 100e4fd9707SSerge Seminrequired: 101e4fd9707SSerge Semin - compatible 102e4fd9707SSerge Semin - "#interrupt-cells" 103e4fd9707SSerge Semin - interrupt-controller 104e4fd9707SSerge Semin 105e4fd9707SSerge Seminexamples: 106e4fd9707SSerge Semin - | 107e4fd9707SSerge Semin #include <dt-bindings/interrupt-controller/mips-gic.h> 108e4fd9707SSerge Semin #include <dt-bindings/interrupt-controller/irq.h> 109e4fd9707SSerge Semin 110e4fd9707SSerge Semin interrupt-controller@1bdc0000 { 111e4fd9707SSerge Semin compatible = "mti,gic"; 112e4fd9707SSerge Semin reg = <0x1bdc0000 0x20000>; 113e4fd9707SSerge Semin interrupt-controller; 114e4fd9707SSerge Semin #interrupt-cells = <3>; 115e4fd9707SSerge Semin mti,reserved-cpu-vectors = <7>; 116e4fd9707SSerge Semin mti,reserved-ipi-vectors = <40 8>; 117e4fd9707SSerge Semin 118e4fd9707SSerge Semin timer { 119e4fd9707SSerge Semin compatible = "mti,gic-timer"; 120e4fd9707SSerge Semin interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 121e4fd9707SSerge Semin clock-frequency = <50000000>; 122e4fd9707SSerge Semin }; 123e4fd9707SSerge Semin }; 124e4fd9707SSerge Semin - | 125e4fd9707SSerge Semin #include <dt-bindings/interrupt-controller/mips-gic.h> 126e4fd9707SSerge Semin #include <dt-bindings/interrupt-controller/irq.h> 127e4fd9707SSerge Semin 128e4fd9707SSerge Semin interrupt-controller@1bdc0000 { 129e4fd9707SSerge Semin compatible = "mti,gic"; 130e4fd9707SSerge Semin reg = <0x1bdc0000 0x20000>; 131e4fd9707SSerge Semin interrupt-controller; 132e4fd9707SSerge Semin #interrupt-cells = <3>; 133e4fd9707SSerge Semin 134e4fd9707SSerge Semin timer { 135e4fd9707SSerge Semin compatible = "mti,gic-timer"; 136e4fd9707SSerge Semin interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 137e4fd9707SSerge Semin clocks = <&cpu_pll>; 138e4fd9707SSerge Semin }; 139e4fd9707SSerge Semin }; 140e4fd9707SSerge Semin - | 141e4fd9707SSerge Semin interrupt-controller { 142e4fd9707SSerge Semin compatible = "mti,gic"; 143e4fd9707SSerge Semin interrupt-controller; 144e4fd9707SSerge Semin #interrupt-cells = <3>; 145e4fd9707SSerge Semin }; 146e4fd9707SSerge Semin... 147