xref: /linux/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microsemi Ocelot SoC ICPU Interrupt Controller
8
9maintainers:
10  - Alexandre Belloni <alexandre.belloni@bootlin.com>
11
12allOf:
13  - $ref: /schemas/interrupt-controller.yaml#
14
15description: |
16  the Microsemi Ocelot interrupt controller that is part of the
17  ICPU. It is connected directly to the MIPS core interrupt
18  controller.
19
20properties:
21  compatible:
22    items:
23      - enum:
24          - mscc,jaguar2-icpu-intr
25          - mscc,luton-icpu-intr
26          - mscc,ocelot-icpu-intr
27          - mscc,serval-icpu-intr
28
29  '#interrupt-cells':
30    const: 1
31
32  '#address-cells':
33    const: 0
34
35  interrupt-controller: true
36
37  reg:
38    maxItems: 1
39
40  interrupts:
41    maxItems: 1
42
43required:
44  - compatible
45  - '#interrupt-cells'
46  - '#address-cells'
47  - interrupt-controller
48  - reg
49
50additionalProperties: false
51
52examples:
53  - |
54    intc: interrupt-controller@70000070 {
55        compatible = "mscc,ocelot-icpu-intr";
56        reg = <0x70000070 0x70>;
57        #interrupt-cells = <1>;
58        #address-cells = <0>;
59        interrupt-controller;
60        interrupt-parent = <&cpuintc>;
61        interrupts = <2>;
62    };
63...
64