1 2* Marvell ODMI for MSI support 3 4Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller 5which can be used by on-board peripheral for MSI interrupts. 6 7Required properties: 8 9- compatible : The value here should contain: 10 11 "marvell,ap806-odmi-controller", "marvell,odmi-controller". 12 13- interrupt,controller : Identifies the node as an interrupt controller. 14 15- msi-controller : Identifies the node as an MSI controller. 16 17- marvell,odmi-frames : Number of ODMI frames available. Each frame 18 provides a number of events. 19 20- reg : List of register definitions, one for each 21 ODMI frame. 22 23- marvell,spi-base : List of GIC base SPI interrupts, one for each 24 ODMI frame. Those SPI interrupts are 0-based, 25 i.e marvell,spi-base = <128> will use SPI #96. 26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml 27 for details about the GIC Device Tree binding. 28 29Example: 30 31 odmi: odmi@300000 { 32 compatible = "marvell,ap806-odmi-controller", 33 "marvell,odmi-controller"; 34 interrupt-controller; 35 msi-controller; 36 marvell,odmi-frames = <4>; 37 reg = <0x300000 0x4000>, 38 <0x304000 0x4000>, 39 <0x308000 0x4000>, 40 <0x30C000 0x4000>; 41 marvell,spi-base = <128>, <136>, <144>, <152>; 42 }; 43