1*f7e642bcSMarek Behún# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*f7e642bcSMarek Behún%YAML 1.2 3*f7e642bcSMarek Behún--- 4*f7e642bcSMarek Behún$id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml# 5*f7e642bcSMarek Behún$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f7e642bcSMarek Behún 7*f7e642bcSMarek Behúntitle: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller 8*f7e642bcSMarek Behún 9*f7e642bcSMarek Behúnmaintainers: 10*f7e642bcSMarek Behún - Marek Behún <kabel@kernel.org> 11*f7e642bcSMarek Behún 12*f7e642bcSMarek Behúndescription: | 13*f7e642bcSMarek Behún The top-level interrupt controller on Marvell Armada 370 and XP. On these 14*f7e642bcSMarek Behún platforms it also provides inter-processor interrupts. 15*f7e642bcSMarek Behún 16*f7e642bcSMarek Behún On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC. 17*f7e642bcSMarek Behún 18*f7e642bcSMarek Behún Provides MSI handling for the PCIe controllers. 19*f7e642bcSMarek Behún 20*f7e642bcSMarek Behúnproperties: 21*f7e642bcSMarek Behún compatible: 22*f7e642bcSMarek Behún const: marvell,mpic 23*f7e642bcSMarek Behún 24*f7e642bcSMarek Behún reg: 25*f7e642bcSMarek Behún items: 26*f7e642bcSMarek Behún - description: main registers 27*f7e642bcSMarek Behún - description: per-cpu registers 28*f7e642bcSMarek Behún 29*f7e642bcSMarek Behún interrupts: 30*f7e642bcSMarek Behún items: 31*f7e642bcSMarek Behún - description: | 32*f7e642bcSMarek Behún Parent interrupt on platforms where MPIC is not the top-level 33*f7e642bcSMarek Behún interrupt controller. 34*f7e642bcSMarek Behún 35*f7e642bcSMarek Behún interrupt-controller: true 36*f7e642bcSMarek Behún 37*f7e642bcSMarek Behún '#interrupt-cells': 38*f7e642bcSMarek Behún const: 1 39*f7e642bcSMarek Behún 40*f7e642bcSMarek Behún msi-controller: true 41*f7e642bcSMarek Behún 42*f7e642bcSMarek Behúnrequired: 43*f7e642bcSMarek Behún - compatible 44*f7e642bcSMarek Behún - reg 45*f7e642bcSMarek Behún - interrupt-controller 46*f7e642bcSMarek Behún - '#interrupt-cells' 47*f7e642bcSMarek Behún - msi-controller 48*f7e642bcSMarek Behún 49*f7e642bcSMarek BehúnadditionalProperties: false 50*f7e642bcSMarek Behún 51*f7e642bcSMarek Behúnexamples: 52*f7e642bcSMarek Behún - | 53*f7e642bcSMarek Behún #include <dt-bindings/interrupt-controller/arm-gic.h> 54*f7e642bcSMarek Behún #include <dt-bindings/interrupt-controller/irq.h> 55*f7e642bcSMarek Behún 56*f7e642bcSMarek Behún interrupt-controller@20a00 { 57*f7e642bcSMarek Behún compatible = "marvell,mpic"; 58*f7e642bcSMarek Behún reg = <0x20a00 0x2d0>, <0x21070 0x58>; 59*f7e642bcSMarek Behún interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 60*f7e642bcSMarek Behún interrupt-controller; 61*f7e642bcSMarek Behún #interrupt-cells = <1>; 62*f7e642bcSMarek Behún msi-controller; 63*f7e642bcSMarek Behún }; 64