xref: /linux/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt (revision e5451c8f8330e03ad3cfa16048b4daf961af434f)
1*9dbd90f1SSebastian HesselbarthMarvell Orion SoC interrupt controllers
2*9dbd90f1SSebastian Hesselbarth
3*9dbd90f1SSebastian Hesselbarth* Main interrupt controller
4*9dbd90f1SSebastian Hesselbarth
5*9dbd90f1SSebastian HesselbarthRequired properties:
6*9dbd90f1SSebastian Hesselbarth- compatible: shall be "marvell,orion-intc"
7*9dbd90f1SSebastian Hesselbarth- reg: base address(es) of interrupt registers starting with CAUSE register
8*9dbd90f1SSebastian Hesselbarth- interrupt-controller: identifies the node as an interrupt controller
9*9dbd90f1SSebastian Hesselbarth- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
10*9dbd90f1SSebastian Hesselbarth
11*9dbd90f1SSebastian HesselbarthThe interrupt sources map to the corresponding bits in the interrupt
12*9dbd90f1SSebastian Hesselbarthregisters, i.e.
13*9dbd90f1SSebastian Hesselbarth- 0 maps to bit 0 of first base address,
14*9dbd90f1SSebastian Hesselbarth- 1 maps to bit 1 of first base address,
15*9dbd90f1SSebastian Hesselbarth- 32 maps to bit 0 of second base address, and so on.
16*9dbd90f1SSebastian Hesselbarth
17*9dbd90f1SSebastian HesselbarthExample:
18*9dbd90f1SSebastian Hesselbarth	intc: interrupt-controller {
19*9dbd90f1SSebastian Hesselbarth		compatible = "marvell,orion-intc";
20*9dbd90f1SSebastian Hesselbarth		interrupt-controller;
21*9dbd90f1SSebastian Hesselbarth		#interrupt-cells = <1>;
22*9dbd90f1SSebastian Hesselbarth		 /* Dove has 64 first level interrupts */
23*9dbd90f1SSebastian Hesselbarth		reg = <0x20200 0x10>, <0x20210 0x10>;
24*9dbd90f1SSebastian Hesselbarth	};
25*9dbd90f1SSebastian Hesselbarth
26*9dbd90f1SSebastian Hesselbarth* Bridge interrupt controller
27*9dbd90f1SSebastian Hesselbarth
28*9dbd90f1SSebastian HesselbarthRequired properties:
29*9dbd90f1SSebastian Hesselbarth- compatible: shall be "marvell,orion-bridge-intc"
30*9dbd90f1SSebastian Hesselbarth- reg: base address of bridge interrupt registers starting with CAUSE register
31*9dbd90f1SSebastian Hesselbarth- interrupts: bridge interrupt of the main interrupt controller
32*9dbd90f1SSebastian Hesselbarth- interrupt-controller: identifies the node as an interrupt controller
33*9dbd90f1SSebastian Hesselbarth- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
34*9dbd90f1SSebastian Hesselbarth
35*9dbd90f1SSebastian HesselbarthOptional properties:
36*9dbd90f1SSebastian Hesselbarth- marvell,#interrupts: number of interrupts provided by bridge interrupt
37*9dbd90f1SSebastian Hesselbarth      controller, defaults to 32 if not set
38*9dbd90f1SSebastian Hesselbarth
39*9dbd90f1SSebastian HesselbarthExample:
40*9dbd90f1SSebastian Hesselbarth	bridge_intc: interrupt-controller {
41*9dbd90f1SSebastian Hesselbarth		compatible = "marvell,orion-bridge-intc";
42*9dbd90f1SSebastian Hesselbarth		interrupt-controller;
43*9dbd90f1SSebastian Hesselbarth		#interrupt-cells = <1>;
44*9dbd90f1SSebastian Hesselbarth		reg = <0x20110 0x8>;
45*9dbd90f1SSebastian Hesselbarth		interrupts = <0>;
46*9dbd90f1SSebastian Hesselbarth		/* Dove bridge provides 5 interrupts */
47*9dbd90f1SSebastian Hesselbarth		marvell,#interrupts = <5>;
48*9dbd90f1SSebastian Hesselbarth	};
49