xref: /linux/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml (revision 2ff81fe310167349ea17c8b2b1d8fb2bc2d755ae) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Loongson Local I/O Interrupt Controller
8
9maintainers:
10  - Jiaxun Yang <jiaxun.yang@flygoat.com>
11
12description: |
13  This interrupt controller is found in the Loongson-3 family of chips and
14  Loongson-2K series chips, as the primary package interrupt controller which
15  can route local I/O interrupt to interrupt lines of cores.
16  Be aware of the following points.
17  1.The Loongson-2K0500 is a single core CPU;
18  2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
19    need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
20    sources respectively.
21
22allOf:
23  - $ref: /schemas/interrupt-controller.yaml#
24
25properties:
26  compatible:
27    enum:
28      - loongson,liointc-1.0
29      - loongson,liointc-1.0a
30      - loongson,liointc-2.0
31
32  reg:
33    minItems: 1
34    maxItems: 3
35
36  reg-names:
37    items:
38      - const: main
39      - const: isr0
40      - const: isr1
41    minItems: 2
42
43  '#address-cells':
44    const: 0
45
46  interrupt-controller: true
47
48  interrupts:
49    description:
50      Interrupt source of the CPU interrupts.
51    minItems: 1
52    maxItems: 4
53
54  interrupt-names:
55    description: List of names for the parent interrupts.
56    items:
57      pattern: int[0-3]
58    minItems: 1
59    maxItems: 4
60
61  '#interrupt-cells':
62    const: 2
63
64  loongson,parent_int_map:
65    description: |
66      This property points how the children interrupts will be mapped into CPU
67      interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
68      and each bit in the cell refers to a child interrupt from 0 to 31.
69      If a CPU interrupt line didn't connect with liointc, then keep its
70      cell with zero.
71    $ref: /schemas/types.yaml#/definitions/uint32-array
72    minItems: 4
73    maxItems: 4
74
75required:
76  - compatible
77  - reg
78  - interrupts
79  - interrupt-names
80  - interrupt-controller
81  - '#interrupt-cells'
82  - loongson,parent_int_map
83
84unevaluatedProperties: false
85
86if:
87  properties:
88    compatible:
89      contains:
90        enum:
91          - loongson,liointc-2.0
92
93then:
94  properties:
95    reg:
96      minItems: 2
97      maxItems: 3
98
99  required:
100    - reg-names
101
102else:
103  properties:
104    reg:
105      maxItems: 1
106
107examples:
108  - |
109    iointc: interrupt-controller@3ff01400 {
110      compatible = "loongson,liointc-1.0";
111      reg = <0x3ff01400 0x64>;
112
113      interrupt-controller;
114      #interrupt-cells = <2>;
115
116      interrupt-parent = <&cpuintc>;
117      interrupts = <2>, <3>;
118      interrupt-names = "int0", "int1";
119
120      loongson,parent_int_map = <0xf0ffffff>, /* int0 */
121                                <0x0f000000>, /* int1 */
122                                <0x00000000>, /* int2 */
123                                <0x00000000>; /* int3 */
124
125    };
126
127...
128