1b6280c8bSJiaxun Yang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b6280c8bSJiaxun Yang%YAML 1.2 3b6280c8bSJiaxun Yang--- 443d78445SRob Herring$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml# 543d78445SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6b6280c8bSJiaxun Yang 7b6280c8bSJiaxun Yangtitle: Loongson Local I/O Interrupt Controller 8b6280c8bSJiaxun Yang 9b6280c8bSJiaxun Yangmaintainers: 10b6280c8bSJiaxun Yang - Jiaxun Yang <jiaxun.yang@flygoat.com> 11b6280c8bSJiaxun Yang 12b6280c8bSJiaxun Yangdescription: | 13f4dee5d8SQing Zhang This interrupt controller is found in the Loongson-3 family of chips and 14aaeebb3eSBinbin Zhou Loongson-2K series chips, as the primary package interrupt controller which 15f4dee5d8SQing Zhang can route local I/O interrupt to interrupt lines of cores. 16aaeebb3eSBinbin Zhou Be aware of the following points. 17aaeebb3eSBinbin Zhou 1.The Loongson-2K0500 is a single core CPU; 18aaeebb3eSBinbin Zhou 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we 19aaeebb3eSBinbin Zhou need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt 20aaeebb3eSBinbin Zhou sources respectively. 21b6280c8bSJiaxun Yang 22b6280c8bSJiaxun YangallOf: 23b6280c8bSJiaxun Yang - $ref: /schemas/interrupt-controller.yaml# 24b6280c8bSJiaxun Yang 25b6280c8bSJiaxun Yangproperties: 26b6280c8bSJiaxun Yang compatible: 271c3ac086SRob Herring enum: 281c3ac086SRob Herring - loongson,liointc-1.0 291c3ac086SRob Herring - loongson,liointc-1.0a 301c3ac086SRob Herring - loongson,liointc-2.0 31b6280c8bSJiaxun Yang 32b6280c8bSJiaxun Yang reg: 33f4dee5d8SQing Zhang minItems: 1 34f4dee5d8SQing Zhang maxItems: 3 35f4dee5d8SQing Zhang 36f4dee5d8SQing Zhang reg-names: 37f4dee5d8SQing Zhang items: 38f4dee5d8SQing Zhang - const: main 39f4dee5d8SQing Zhang - const: isr0 40f4dee5d8SQing Zhang - const: isr1 41aaeebb3eSBinbin Zhou minItems: 2 42b6280c8bSJiaxun Yang 43b6280c8bSJiaxun Yang interrupt-controller: true 44b6280c8bSJiaxun Yang 45b6280c8bSJiaxun Yang interrupts: 46b6280c8bSJiaxun Yang description: 47b6280c8bSJiaxun Yang Interrupt source of the CPU interrupts. 48b6280c8bSJiaxun Yang minItems: 1 49b6280c8bSJiaxun Yang maxItems: 4 50b6280c8bSJiaxun Yang 51b6280c8bSJiaxun Yang interrupt-names: 52b6280c8bSJiaxun Yang description: List of names for the parent interrupts. 53b6280c8bSJiaxun Yang items: 54*db8ce240SBinbin Zhou pattern: int[0-3] 55b6280c8bSJiaxun Yang minItems: 1 56*db8ce240SBinbin Zhou maxItems: 4 57b6280c8bSJiaxun Yang 58b6280c8bSJiaxun Yang '#interrupt-cells': 59b6280c8bSJiaxun Yang const: 2 60b6280c8bSJiaxun Yang 6143d78445SRob Herring loongson,parent_int_map: 62b6280c8bSJiaxun Yang description: | 63b6280c8bSJiaxun Yang This property points how the children interrupts will be mapped into CPU 64b6280c8bSJiaxun Yang interrupt lines. Each cell refers to a parent interrupt line from 0 to 3 65f7dcfea3STiezhu Yang and each bit in the cell refers to a child interrupt from 0 to 31. 66f7dcfea3STiezhu Yang If a CPU interrupt line didn't connect with liointc, then keep its 67b6280c8bSJiaxun Yang cell with zero. 683d21a460SRob Herring $ref: /schemas/types.yaml#/definitions/uint32-array 693d21a460SRob Herring minItems: 4 70b6280c8bSJiaxun Yang maxItems: 4 71b6280c8bSJiaxun Yang 72b6280c8bSJiaxun Yangrequired: 73b6280c8bSJiaxun Yang - compatible 74b6280c8bSJiaxun Yang - reg 75b6280c8bSJiaxun Yang - interrupts 76*db8ce240SBinbin Zhou - interrupt-names 77b6280c8bSJiaxun Yang - interrupt-controller 78b6280c8bSJiaxun Yang - '#interrupt-cells' 7943d78445SRob Herring - loongson,parent_int_map 80b6280c8bSJiaxun Yang 81b6280c8bSJiaxun Yang 826fdc6e23SRob HerringunevaluatedProperties: false 836fdc6e23SRob Herring 84f4dee5d8SQing Zhangif: 85f4dee5d8SQing Zhang properties: 86f4dee5d8SQing Zhang compatible: 87f4dee5d8SQing Zhang contains: 88f4dee5d8SQing Zhang enum: 89f4dee5d8SQing Zhang - loongson,liointc-2.0 90f4dee5d8SQing Zhang 91f4dee5d8SQing Zhangthen: 92f4dee5d8SQing Zhang properties: 93f4dee5d8SQing Zhang reg: 94aaeebb3eSBinbin Zhou minItems: 2 95aaeebb3eSBinbin Zhou maxItems: 3 96f4dee5d8SQing Zhang 97f4dee5d8SQing Zhang required: 98f4dee5d8SQing Zhang - reg-names 99f4dee5d8SQing Zhang 100f4dee5d8SQing Zhangelse: 101f4dee5d8SQing Zhang properties: 102f4dee5d8SQing Zhang reg: 103f4dee5d8SQing Zhang maxItems: 1 104f4dee5d8SQing Zhang 105b6280c8bSJiaxun Yangexamples: 106b6280c8bSJiaxun Yang - | 107b6280c8bSJiaxun Yang iointc: interrupt-controller@3ff01400 { 108b6280c8bSJiaxun Yang compatible = "loongson,liointc-1.0"; 109b6280c8bSJiaxun Yang reg = <0x3ff01400 0x64>; 110b6280c8bSJiaxun Yang 111b6280c8bSJiaxun Yang interrupt-controller; 112b6280c8bSJiaxun Yang #interrupt-cells = <2>; 113b6280c8bSJiaxun Yang 114b6280c8bSJiaxun Yang interrupt-parent = <&cpuintc>; 115b6280c8bSJiaxun Yang interrupts = <2>, <3>; 116b6280c8bSJiaxun Yang interrupt-names = "int0", "int1"; 117b6280c8bSJiaxun Yang 118b6280c8bSJiaxun Yang loongson,parent_int_map = <0xf0ffffff>, /* int0 */ 119b6280c8bSJiaxun Yang <0x0f000000>, /* int1 */ 120b6280c8bSJiaxun Yang <0x00000000>, /* int2 */ 121b6280c8bSJiaxun Yang <0x00000000>; /* int3 */ 122b6280c8bSJiaxun Yang 123b6280c8bSJiaxun Yang }; 124b6280c8bSJiaxun Yang 125b6280c8bSJiaxun Yang... 126