xref: /linux/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml (revision aaeebb3ea4f2d6674b0fbc8bd48bf8862309f191)
1b6280c8bSJiaxun Yang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2b6280c8bSJiaxun Yang%YAML 1.2
3b6280c8bSJiaxun Yang---
443d78445SRob Herring$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
543d78445SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml#
6b6280c8bSJiaxun Yang
7b6280c8bSJiaxun Yangtitle: Loongson Local I/O Interrupt Controller
8b6280c8bSJiaxun Yang
9b6280c8bSJiaxun Yangmaintainers:
10b6280c8bSJiaxun Yang  - Jiaxun Yang <jiaxun.yang@flygoat.com>
11b6280c8bSJiaxun Yang
12b6280c8bSJiaxun Yangdescription: |
13f4dee5d8SQing Zhang  This interrupt controller is found in the Loongson-3 family of chips and
14*aaeebb3eSBinbin Zhou  Loongson-2K series chips, as the primary package interrupt controller which
15f4dee5d8SQing Zhang  can route local I/O interrupt to interrupt lines of cores.
16*aaeebb3eSBinbin Zhou  Be aware of the following points.
17*aaeebb3eSBinbin Zhou  1.The Loongson-2K0500 is a single core CPU;
18*aaeebb3eSBinbin Zhou  2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
19*aaeebb3eSBinbin Zhou    need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
20*aaeebb3eSBinbin Zhou    sources respectively.
21b6280c8bSJiaxun Yang
22b6280c8bSJiaxun YangallOf:
23b6280c8bSJiaxun Yang  - $ref: /schemas/interrupt-controller.yaml#
24b6280c8bSJiaxun Yang
25b6280c8bSJiaxun Yangproperties:
26b6280c8bSJiaxun Yang  compatible:
271c3ac086SRob Herring    enum:
281c3ac086SRob Herring      - loongson,liointc-1.0
291c3ac086SRob Herring      - loongson,liointc-1.0a
301c3ac086SRob Herring      - loongson,liointc-2.0
31b6280c8bSJiaxun Yang
32b6280c8bSJiaxun Yang  reg:
33f4dee5d8SQing Zhang    minItems: 1
34f4dee5d8SQing Zhang    maxItems: 3
35f4dee5d8SQing Zhang
36f4dee5d8SQing Zhang  reg-names:
37f4dee5d8SQing Zhang    items:
38f4dee5d8SQing Zhang      - const: main
39f4dee5d8SQing Zhang      - const: isr0
40f4dee5d8SQing Zhang      - const: isr1
41*aaeebb3eSBinbin Zhou    minItems: 2
42b6280c8bSJiaxun Yang
43b6280c8bSJiaxun Yang  interrupt-controller: true
44b6280c8bSJiaxun Yang
45b6280c8bSJiaxun Yang  interrupts:
46b6280c8bSJiaxun Yang    description:
47b6280c8bSJiaxun Yang      Interrupt source of the CPU interrupts.
48b6280c8bSJiaxun Yang    minItems: 1
49b6280c8bSJiaxun Yang    maxItems: 4
50b6280c8bSJiaxun Yang
51b6280c8bSJiaxun Yang  interrupt-names:
52b6280c8bSJiaxun Yang    description: List of names for the parent interrupts.
53b6280c8bSJiaxun Yang    items:
54b6280c8bSJiaxun Yang      - const: int0
55b6280c8bSJiaxun Yang      - const: int1
56b6280c8bSJiaxun Yang      - const: int2
57b6280c8bSJiaxun Yang      - const: int3
58b6280c8bSJiaxun Yang    minItems: 1
59b6280c8bSJiaxun Yang
60b6280c8bSJiaxun Yang  '#interrupt-cells':
61b6280c8bSJiaxun Yang    const: 2
62b6280c8bSJiaxun Yang
6343d78445SRob Herring  loongson,parent_int_map:
64b6280c8bSJiaxun Yang    description: |
65b6280c8bSJiaxun Yang      This property points how the children interrupts will be mapped into CPU
66b6280c8bSJiaxun Yang      interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
67f7dcfea3STiezhu Yang      and each bit in the cell refers to a child interrupt from 0 to 31.
68f7dcfea3STiezhu Yang      If a CPU interrupt line didn't connect with liointc, then keep its
69b6280c8bSJiaxun Yang      cell with zero.
703d21a460SRob Herring    $ref: /schemas/types.yaml#/definitions/uint32-array
713d21a460SRob Herring    minItems: 4
72b6280c8bSJiaxun Yang    maxItems: 4
73b6280c8bSJiaxun Yang
74b6280c8bSJiaxun Yangrequired:
75b6280c8bSJiaxun Yang  - compatible
76b6280c8bSJiaxun Yang  - reg
77b6280c8bSJiaxun Yang  - interrupts
78b6280c8bSJiaxun Yang  - interrupt-controller
79b6280c8bSJiaxun Yang  - '#interrupt-cells'
8043d78445SRob Herring  - loongson,parent_int_map
81b6280c8bSJiaxun Yang
82b6280c8bSJiaxun Yang
836fdc6e23SRob HerringunevaluatedProperties: false
846fdc6e23SRob Herring
85f4dee5d8SQing Zhangif:
86f4dee5d8SQing Zhang  properties:
87f4dee5d8SQing Zhang    compatible:
88f4dee5d8SQing Zhang      contains:
89f4dee5d8SQing Zhang        enum:
90f4dee5d8SQing Zhang          - loongson,liointc-2.0
91f4dee5d8SQing Zhang
92f4dee5d8SQing Zhangthen:
93f4dee5d8SQing Zhang  properties:
94f4dee5d8SQing Zhang    reg:
95*aaeebb3eSBinbin Zhou      minItems: 2
96*aaeebb3eSBinbin Zhou      maxItems: 3
97f4dee5d8SQing Zhang
98f4dee5d8SQing Zhang  required:
99f4dee5d8SQing Zhang    - reg-names
100f4dee5d8SQing Zhang
101f4dee5d8SQing Zhangelse:
102f4dee5d8SQing Zhang  properties:
103f4dee5d8SQing Zhang    reg:
104f4dee5d8SQing Zhang      maxItems: 1
105f4dee5d8SQing Zhang
106b6280c8bSJiaxun Yangexamples:
107b6280c8bSJiaxun Yang  - |
108b6280c8bSJiaxun Yang    iointc: interrupt-controller@3ff01400 {
109b6280c8bSJiaxun Yang      compatible = "loongson,liointc-1.0";
110b6280c8bSJiaxun Yang      reg = <0x3ff01400 0x64>;
111b6280c8bSJiaxun Yang
112b6280c8bSJiaxun Yang      interrupt-controller;
113b6280c8bSJiaxun Yang      #interrupt-cells = <2>;
114b6280c8bSJiaxun Yang
115b6280c8bSJiaxun Yang      interrupt-parent = <&cpuintc>;
116b6280c8bSJiaxun Yang      interrupts = <2>, <3>;
117b6280c8bSJiaxun Yang      interrupt-names = "int0", "int1";
118b6280c8bSJiaxun Yang
119b6280c8bSJiaxun Yang      loongson,parent_int_map = <0xf0ffffff>, /* int0 */
120b6280c8bSJiaxun Yang                                <0x0f000000>, /* int1 */
121b6280c8bSJiaxun Yang                                <0x00000000>, /* int2 */
122b6280c8bSJiaxun Yang                                <0x00000000>; /* int3 */
123b6280c8bSJiaxun Yang
124b6280c8bSJiaxun Yang    };
125b6280c8bSJiaxun Yang
126b6280c8bSJiaxun Yang...
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