xref: /linux/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml (revision 5ef7ce7e81bbc1788a7e24d067f34f591a9508f1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Loongson-3 HyperTransport Interrupt Controller
8
9maintainers:
10  - Jiaxun Yang <jiaxun.yang@flygoat.com>
11
12allOf:
13  - $ref: /schemas/interrupt-controller.yaml#
14
15description: |
16  This interrupt controller is found in the Loongson-3 family of chips to transmit
17  interrupts from PCH PIC connected on HyperTransport bus.
18
19properties:
20  compatible:
21    const: loongson,htpic-1.0
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    minItems: 1
28    maxItems: 4
29    description: |
30      Four parent interrupts that receive chained interrupts.
31
32  interrupt-controller: true
33
34  '#interrupt-cells':
35    const: 1
36
37required:
38  - compatible
39  - reg
40  - interrupts
41  - interrupt-controller
42  - '#interrupt-cells'
43
44examples:
45  - |
46    #include <dt-bindings/interrupt-controller/irq.h>
47    htintc: interrupt-controller@1fb000080 {
48      compatible = "loongson,htintc-1.0";
49      reg = <0xfb000080 0x40>;
50      interrupt-controller;
51      #interrupt-cells = <1>;
52
53      interrupt-parent = <&liointc>;
54      interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
55                    <25 IRQ_TYPE_LEVEL_HIGH>,
56                    <26 IRQ_TYPE_LEVEL_HIGH>,
57                    <27 IRQ_TYPE_LEVEL_HIGH>;
58    };
59...
60