xref: /linux/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml (revision d0e99511834b6828c960e978d9a8cb6e5731250d) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
8
9maintainers:
10  - Rahul Tanwar <rtanwar@maxlinear.com>
11
12description: |
13  Intel's Advanced Programmable Interrupt Controller (APIC) is a
14  family of interrupt controllers. The APIC is a split
15  architecture design, with a local component (LAPIC) integrated
16  into the processor itself and an external I/O APIC. Local APIC
17  (lapic) receives interrupts from the processor's interrupt pins,
18  from internal sources and from an external I/O APIC (ioapic).
19  And it sends these to the processor core for handling.
20  See [1] Chapter 8 for more details.
21
22  Many of the Intel's generic devices like hpet, ioapic, lapic have
23  the ce4100 name in their compatible property names because they
24  first appeared in CE4100 SoC.
25
26  This schema defines bindings for local APIC interrupt controller.
27
28  [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
29
30properties:
31  compatible:
32    const: intel,ce4100-lapic
33
34  reg:
35    maxItems: 1
36
37  interrupt-controller: true
38
39  '#interrupt-cells':
40    const: 2
41
42  intel,virtual-wire-mode:
43    description: Intel defines a few possible interrupt delivery
44      modes. With respect to boot/init time, mainly two interrupt
45      delivery modes are possible.
46      PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
47      Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
48      For ACPI or MPS spec compliant systems, it is figured out by some read
49      only bit field/s available in their respective defined data structures.
50      For OF based systems, it is by default set to PIC mode.
51      But if this optional boolean property is set, then the interrupt delivery
52      mode is configured to virtual wire compatibility mode.
53    type: boolean
54
55required:
56  - compatible
57  - reg
58  - interrupt-controller
59  - '#interrupt-cells'
60
61additionalProperties: false
62
63examples:
64  - |
65    lapic0: interrupt-controller@fee00000 {
66        compatible = "intel,ce4100-lapic";
67        reg = <0xfee00000 0x1000>;
68        interrupt-controller;
69        #interrupt-cells = <2>;
70        intel,virtual-wire-mode;
71    };
72