12b822f47SRahul Tanwar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 22b822f47SRahul Tanwar%YAML 1.2 32b822f47SRahul Tanwar--- 4*43d78445SRob Herring$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml# 5*43d78445SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 62b822f47SRahul Tanwar 72b822f47SRahul Tanwartitle: Intel Local Advanced Programmable Interrupt Controller (LAPIC) 82b822f47SRahul Tanwar 92b822f47SRahul Tanwarmaintainers: 102b822f47SRahul Tanwar - Rahul Tanwar <rtanwar@maxlinear.com> 112b822f47SRahul Tanwar 122b822f47SRahul Tanwardescription: | 132b822f47SRahul Tanwar Intel's Advanced Programmable Interrupt Controller (APIC) is a 142b822f47SRahul Tanwar family of interrupt controllers. The APIC is a split 152b822f47SRahul Tanwar architecture design, with a local component (LAPIC) integrated 162b822f47SRahul Tanwar into the processor itself and an external I/O APIC. Local APIC 172b822f47SRahul Tanwar (lapic) receives interrupts from the processor's interrupt pins, 182b822f47SRahul Tanwar from internal sources and from an external I/O APIC (ioapic). 192b822f47SRahul Tanwar And it sends these to the processor core for handling. 202b822f47SRahul Tanwar See [1] Chapter 8 for more details. 212b822f47SRahul Tanwar 222b822f47SRahul Tanwar Many of the Intel's generic devices like hpet, ioapic, lapic have 232b822f47SRahul Tanwar the ce4100 name in their compatible property names because they 242b822f47SRahul Tanwar first appeared in CE4100 SoC. 252b822f47SRahul Tanwar 262b822f47SRahul Tanwar This schema defines bindings for local APIC interrupt controller. 272b822f47SRahul Tanwar 282b822f47SRahul Tanwar [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf 292b822f47SRahul Tanwar 302b822f47SRahul Tanwarproperties: 312b822f47SRahul Tanwar compatible: 322b822f47SRahul Tanwar const: intel,ce4100-lapic 332b822f47SRahul Tanwar 342b822f47SRahul Tanwar reg: 352b822f47SRahul Tanwar maxItems: 1 362b822f47SRahul Tanwar 372b822f47SRahul Tanwar interrupt-controller: true 382b822f47SRahul Tanwar 392b822f47SRahul Tanwar '#interrupt-cells': 402b822f47SRahul Tanwar const: 2 412b822f47SRahul Tanwar 42b3a9801cSRahul Tanwar intel,virtual-wire-mode: 43b3a9801cSRahul Tanwar description: Intel defines a few possible interrupt delivery 44b3a9801cSRahul Tanwar modes. With respect to boot/init time, mainly two interrupt 45b3a9801cSRahul Tanwar delivery modes are possible. 46b3a9801cSRahul Tanwar PIC Mode - Legacy external 8259 compliant PIC interrupt controller. 47b3a9801cSRahul Tanwar Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. 48b3a9801cSRahul Tanwar For ACPI or MPS spec compliant systems, it is figured out by some read 49b3a9801cSRahul Tanwar only bit field/s available in their respective defined data structures. 50b3a9801cSRahul Tanwar For OF based systems, it is by default set to PIC mode. 51b3a9801cSRahul Tanwar But if this optional boolean property is set, then the interrupt delivery 52b3a9801cSRahul Tanwar mode is configured to virtual wire compatibility mode. 53b3a9801cSRahul Tanwar type: boolean 54b3a9801cSRahul Tanwar 552b822f47SRahul Tanwarrequired: 562b822f47SRahul Tanwar - compatible 572b822f47SRahul Tanwar - reg 582b822f47SRahul Tanwar - interrupt-controller 592b822f47SRahul Tanwar - '#interrupt-cells' 602b822f47SRahul Tanwar 612b822f47SRahul TanwaradditionalProperties: false 622b822f47SRahul Tanwar 632b822f47SRahul Tanwarexamples: 642b822f47SRahul Tanwar - | 652b822f47SRahul Tanwar lapic0: interrupt-controller@fee00000 { 662b822f47SRahul Tanwar compatible = "intel,ce4100-lapic"; 672b822f47SRahul Tanwar reg = <0xfee00000 0x1000>; 682b822f47SRahul Tanwar interrupt-controller; 692b822f47SRahul Tanwar #interrupt-cells = <2>; 70b3a9801cSRahul Tanwar intel,virtual-wire-mode; 712b822f47SRahul Tanwar }; 72