1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Vybrid Miscellaneous System Control - Interrupt Router 8 9description: 10 The MSCM IP contains multiple sub modules, this binding describes the second 11 block of registers which control the interrupt router. The interrupt router 12 allows to configure the recipient of each peripheral interrupt. Furthermore 13 it controls the directed processor interrupts. The module is available in all 14 Vybrid SoC's but is only really useful in dual core configurations (VF6xx 15 which comes with a Cortex-A5/Cortex-M4 combination). 16 17maintainers: 18 - Frank Li <Frank.Li@nxp.com> 19 20properties: 21 compatible: 22 const: fsl,vf610-mscm-ir 23 24 reg: 25 maxItems: 1 26 27 fsl,cpucfg: 28 $ref: /schemas/types.yaml#/definitions/phandle 29 description: 30 The handle to the MSCM CPU configuration node, required 31 to get the current CPU ID 32 33 interrupt-controller: true 34 35 '#interrupt-cells': 36 const: 2 37 description: 38 Two cells, interrupt number and cells. 39 The hardware interrupt number according to interrupt 40 assignment of the interrupt router is required. 41 Flags get passed only when using GIC as parent. Flags 42 encoding as documented by the GIC bindings. 43 44required: 45 - compatible 46 - reg 47 - fsl,cpucfg 48 - interrupt-controller 49 - '#interrupt-cells' 50 51additionalProperties: false 52 53examples: 54 - | 55 interrupt-controller@40001800 { 56 compatible = "fsl,vf610-mscm-ir"; 57 reg = <0x40001800 0x400>; 58 fsl,cpucfg = <&mscm_cpucfg>; 59 interrupt-controller; 60 #interrupt-cells = <2>; 61 interrupt-parent = <&intc>; 62 }; 63