xref: /linux/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml (revision 69f2970aad93758bea863432e49b564e0ba649ca)
1*1693d187SFrank Li# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*1693d187SFrank Li%YAML 1.2
3*1693d187SFrank Li---
4*1693d187SFrank Li$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml#
5*1693d187SFrank Li$schema: http://devicetree.org/meta-schemas/core.yaml#
6*1693d187SFrank Li
7*1693d187SFrank Lititle: Freescale Vybrid Miscellaneous System Control - Interrupt Router
8*1693d187SFrank Li
9*1693d187SFrank Lidescription:
10*1693d187SFrank Li  The MSCM IP contains multiple sub modules, this binding describes the second
11*1693d187SFrank Li  block of registers which control the interrupt router. The interrupt router
12*1693d187SFrank Li  allows to configure the recipient of each peripheral interrupt. Furthermore
13*1693d187SFrank Li  it controls the directed processor interrupts. The module is available in all
14*1693d187SFrank Li  Vybrid SoC's but is only really useful in dual core configurations (VF6xx
15*1693d187SFrank Li  which comes with a Cortex-A5/Cortex-M4 combination).
16*1693d187SFrank Li
17*1693d187SFrank Li
18*1693d187SFrank Limaintainers:
19*1693d187SFrank Li  - Frank Li <Frank.Li@nxp.com>
20*1693d187SFrank Li
21*1693d187SFrank Liproperties:
22*1693d187SFrank Li  compatible:
23*1693d187SFrank Li    const: fsl,vf610-mscm-ir
24*1693d187SFrank Li
25*1693d187SFrank Li  reg:
26*1693d187SFrank Li    maxItems: 1
27*1693d187SFrank Li
28*1693d187SFrank Li  fsl,cpucfg:
29*1693d187SFrank Li    $ref: /schemas/types.yaml#/definitions/phandle
30*1693d187SFrank Li    description:
31*1693d187SFrank Li      The handle to the MSCM CPU configuration node, required
32*1693d187SFrank Li      to get the current CPU ID
33*1693d187SFrank Li
34*1693d187SFrank Li  interrupt-controller: true
35*1693d187SFrank Li
36*1693d187SFrank Li  '#interrupt-cells':
37*1693d187SFrank Li    const: 2
38*1693d187SFrank Li    description:
39*1693d187SFrank Li      Two cells, interrupt number and cells.
40*1693d187SFrank Li      The hardware interrupt number according to interrupt
41*1693d187SFrank Li      assignment of the interrupt router is required.
42*1693d187SFrank Li      Flags get passed only when using GIC as parent. Flags
43*1693d187SFrank Li      encoding as documented by the GIC bindings.
44*1693d187SFrank Li
45*1693d187SFrank Lirequired:
46*1693d187SFrank Li  - compatible
47*1693d187SFrank Li  - reg
48*1693d187SFrank Li  - fsl,cpucfg
49*1693d187SFrank Li  - interrupt-controller
50*1693d187SFrank Li  - '#interrupt-cells'
51*1693d187SFrank Li
52*1693d187SFrank LiadditionalProperties: false
53*1693d187SFrank Li
54*1693d187SFrank Liexamples:
55*1693d187SFrank Li  - |
56*1693d187SFrank Li    interrupt-controller@40001800 {
57*1693d187SFrank Li        compatible = "fsl,vf610-mscm-ir";
58*1693d187SFrank Li        reg = <0x40001800 0x400>;
59*1693d187SFrank Li        fsl,cpucfg = <&mscm_cpucfg>;
60*1693d187SFrank Li        interrupt-controller;
61*1693d187SFrank Li        #interrupt-cells = <2>;
62*1693d187SFrank Li        interrupt-parent = <&intc>;
63*1693d187SFrank Li    };
64